PRELIMINARY INFORMATION - COMPANY CONFIDENTIAL PI3EQX5801 5.0Gbps, 1-Lane, PCIe 2.0 ReDriver 2 with I C Programming Interface Features Description PCIe 2.0 compatible Pericom Semiconductors PI3EQX5801 is a low power, high performance 5.0 Gbps signal ReDriver designed specicfi ally Two 5.0Gbps differential signal pairs for the PCIe 2.0 protocol. The device provides programmable Adjustable Receiver Equalization equalization, De-Emphasis, and output swing controls to op- 100 Differential CML I/Os timize performance over a variety of physical mediums by Pin Configured Output Emphasis and Output Swing Control 1.2V reducing Inter-Symbol Interference. PI3EQX5801 supports two Operation Input signal level detect and squelch for each channel 100 Differential CML data I/Os between the Protocol ASIC to a Automatic Receiver Detect switch fabric, over cable, or to extend the signals across other dis- 2019181716 AI+ 1 15 AO+ Low Power : ~330mW (3.3V)/~150mW (1.5V) tant data pathways on the users platform. e Th integrated equal - AI- 2 14 AO- EN A 3 ization circuitry provides flexibility with signal integrity of the 13 EN B Industrial Temp Support -4GND0C~ +85C BO- 4 12 BI- signal before the ReDriver. A low-level input signal detection and 5 Stand-by MoBO+de Power Down Stat11e BI+ 6 7 8 9 10 output squelch function is provided for each channel. Two power options: 3.3V or 1.5V Packaging: 20-Pin TQFN (4x4mm) When the channels are enabled, EN = 0, and operating, that chan- nels input signal level (on xI+/-) determines whether the output is active. If the input signal level of the channel falls below the active Figure 1. Pin Diagram (Top Side View) threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to signal conditioning, when EN = 1, the device enters a low power standby mode. e Th PI3EQX5801 also 2 2 includes a fully programmable I C interface. When I C control 3.3V / 1.5V Operation mode is enabled, I2C EN = 1, equalization, output swing, and de-emphasis settings can be adjusted by programming the re- 2019181716 AI+ 1 lated registers. 15 AO+ AI- 2 14 AO- EN 3 13 I2C EN GND 4 12 BO- BI- 5 11 BO+ BI+ 6 7 8 9 10 Figure 3 Figure 2. Block Diagram PCIe 2.0 ReDriver Signal Detection Blade Server CML Blade Server CML TXP RXP PCIe 2.0 Cable Limiting Equalizer Amp RXN TXN EQ x - Repeated 2 times - Power Management www.pericom.com P-0.1 02/19/13 13-0018 1 PI3EQX6701PI3EQX7711 VDD33 / VDD1.5 VDD12 DNC / VDD1.5 VDD12 EQ B OS A SCL EQ B RxDet DE B DE B / A0 DE A / SDA DE A EQ A RES EQ A OS B / A1 DNC / VDD1.5 VDD3.3 / VDD1.5 VDD12 VDD12PRELIMINARY INFORMATION - COMPANY CONFIDENTIAL PI3EQX5801 2 5.0Gbps, 1-Lane, PCIe 2.0 ReDriver with I C Programming Interface Pin Description Pin Pin Name Type Description 1 AI+ 2 AI- CML input channels with selectable input termination between 50 to internal V or bias Input 11 BI+ internal 60k pull-down to GND. 12 BI- Chip Enable. When the pin is drivenLo, chip is in normal operation. When the pin is 3 EN Input driven High, chip is in power down mode. With internal 200k pull-down resistor. 4 BO- 5 BO+ Selectable output termination between 50 to internal V 2k to internal V , or bias bias Output 14 AO- Hi-Z. 15 AO+ 6 DNC / DNC / Do Not Connect / 1.5V Voltage Supply 16 VDD1.5 Power Set the equalization of two channels. These are Tri-level input pins. When set toHIG 7 EQ B, Input the pin becomes Logic1 when set toope, the pin becomesope, when set to 17 EQ A lo, the pin becomes logic0 . Please refer to Mode Adjustment on page 3. Set the de-emphasis of the output CML buffer for Channel B. This is a Tri-level input pins When set tohig, the pin becomes logic1 when set toope, the pin becomes ope when set tolo, the pin becomes logic0 . Please refer to Mode Adjustment on 8 DE B / A0 Input page 3. 2 2 This pin is also used for I C programming interface. When set tohig or floating I C 2 address bit A0 is set to1 . When set tolo I C address bit A0 is set to0 . Set the output swing of Channel B. This is a Tri-level input pins When set toHIG, the pin becomes Logic1 when set toope, the pin becomesope, when set tolo, the pin becomes logic0 . 9 OS B / A1 Input 2 2 This pin is also used for I C programming interface. When set tohig or floating I C 2 address bit A1 is set to1 . When set tolo I C address bit A1 is set to0 . 10 VDD3.3 / Power 3.3V Voltage Supply / 1.5V Voltage Supply 20 VDD1.5 2 2 I C Control Enable. When the pin is driven High, chip is in I C Control Mode. When 13 I2C EN Input the pin is driven Low, chip is in pin strap control mode. With internal 200k pull-down resistor. Set the de-emphasis of the output CML buffer for Channel A. These is a Tri-level input pin. When set tohig, the pin becomes logic1 when set toope, the pin becomes DE A / Input /ope when set tolo, the pin becomes logic0 . Please refer to Mode Adjustment on 18 SDA Output page 3. 2 This pin is also used as Data Line for I C programming interface 3.3V tolerant. Set the output swing of Channel A. This is a Tri-level input pins When set toHIG, the pin becomes Logic1 when set toope, the pin becomesope, when set tolo, OS A / 19 Input the pin becomes logic0 . SCL 2 This pin is also used as Clock Line for I C programming interface3.3 tolerant. Center Pad GND GND Supply Ground. www.pericom.com P-0.1 02/19/13 13-0018 2