CYDMX128A16-65BVXI

THIS SPEC IS OBSOLETE Spec No: 001-08090 Spec Title: CYDMX256A16/CYDMX256B16/CYDMX128A16/ CYDMX128B16/CYDMX064A16/CYDMX064B16, 16K/8K/4K X 16 MOBL(R) ADM ASYNCHRONOUS DUAL-PORT STATIC RAM. Replaced by: None CYDMX256A16/CYDMX256B16 CYDMX128A16/CYDMX128B16 CYDMX064A16/CYDMX064B16 16K/8K/4K 16 MoBL ADM Asynchronous Dual-Port Static RAM 16K/8K/4K 16 MoBL ADM Asynchronous Dual-Port Static RAM Ultra low operating power Features Active: I = 15 mA (typical) at 90 ns CC True dual-ported memory block that allow simultaneous Active: I = 25 mA (typical) at 65 ns CC independent access Standby: I = 2 A (typical) SB3 One port with dedicated time multiplexed address and data Port independent power-down (ADM) interface One port configurable to standard SRAM or time multiplexed On-chip arbitration logic address and data interface Mailbox interrupt for port to port communication 16 K/8 K/4 K 16 memory configuration Input Read and Output Drive registers High speed access Upper byte and lower byte control 65 ns or 90 ns ADM interface 40 ns or 60 ns standard SRAM interface Small package: 6 6 mm, 100-ball Pb-free BGA Fully asynchronous operation Industrial temperature range Port independent 1.8 V, 2.5 V, and 3.0 V IOs Block Diagram IRR1-IRR0 note 2 SFEN IRR/ODR ODR4-ODR0 DataL<15..0> DataR<15..0> I/OL15-I/OL8 I/OR15-I/OR8 Mux ed Mux ed I/OL7-I/OL0 Dual Ported I/OR7-I/OR0 Address / Address/ Memory Array Data Data ADV L ADV R AddrL<13..0> 16k/8k/4k x 16 AddrR<13..0> I/O Control I/O Control UB L UB R LB L LB R A13-A0 note 1 Address Address MSEL Decode Decode CS L CS R OE L Control Logic OE R WE L WE R BUSY L BUSY R INT L INT R Notes 1. A13-A0 for CYDMX256A16 and CYDMX256B16 A12-A0 for CYDMX128A16 and CYDMX128B16 and A11-A0 for CYDMX064A16 and CYDMX064B16. 2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-08090 Rev. *K Revised March 1, 2019