CY7C1165KV18-400BZXC

CY7C1161KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles: Supports concurrent transactions CY7C1163KV18 1M 18 550-MHz clock for high bandwidth CY7C1165KV18 512K 36 Four-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz The CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ Available in 2.5 clock cycle latency architecture. Similar to QDR II architecture, QDR II+ architecture Two input clocks (K and K) for precise DDR timing consists of two separate ports: the read port and the write port to SRAM uses rising edges only access the memory array. The read port has dedicated data outputs to support read operations and the write port has Echo clocks (CQ and CQ) simplify data capture in high speed dedicated data inputs to support write operations. QDR II+ systems architecture has separate data inputs and data outputs to Data valid pin (QVLD) to indicate valid data on the output completely eliminate the need to turnaround the data bus that exists with common I/O devices. Each port is accessed through Single multiplexed address input bus latches address inputs for read and write ports a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Separate port selects for depth expansion Accesses to the QDR II+ read and write ports are completely Synchronous internally self-timed writes independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each QDR II+ operates with 2.5 cycle read latency when DOFF is address location is associated with four 18-bit words asserted HIGH (CY7C1163KV18), or 36-bit words (CY7C1165KV18) that burst Operates similar to QDR I device with one cycle read latency sequentially into or out of the device. Because data is transferred when DOFF is asserted LOW into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while Available in 18, and 36 configurations simplifying system design by eliminating bus turnarounds. Full data coherency, providing most current data Depth expansion is accomplished with port selects, which 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V DD DDQ DD enables each port to operate independently. Supports both 1.5 V and 1.8 V I/O supply All synchronous inputs pass through input registers controlled by HSTL inputs and variable drive HSTL output buffers the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are Available in 165-ball FBGA package (13 15 1.4 mm) conducted with on-chip synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 450 MHz 400 MHz Unit Maximum operating frequency 550 450 400 MHz Maximum operating current 18 780 670 610 mA 36 1100 Not Offered 850 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-58911 Rev. *I Revised January 3, 2018256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array CY7C1163KV18/CY7C1165KV18 Logic Block Diagram CY7C1163KV18 18 D 17:0 Write Write Write Write 18 Address A Reg Reg Reg Reg (17:0) Register 18 Address A (17:0) Register K RPS Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control WPS 18 Logic 18 18 36 BWS Q Reg. 1:0 17:0 18 QVLD Logic Block Diagram CY7C1165KV18 36 D 35:0 Write Write Write Write 17 Address A Reg Reg Reg Reg (16:0) Register 17 Address A (16:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 144 V 72 REF CQ 36 Reg. Reg. Control WPS 36 Logic 36 72 36 BWS Q 3:0 Reg. 35:0 36 QVLD Document Number: 001-58911 Rev. *I Page 2 of 30 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode