CMX602B CML Microcircuits Calling Line Identifier COMMUNICATION SEMICONDUCTORS plus Call Waiting (Type II) D/602B/2 September 2003 Features Applications CLI and CIDCW System Operation CLI and CIDCW Adjunct Boxes Low Power Operation 0.5mA at 2.7V CLI and CIDCW Feature Phones Zero-Power Ring or Line Reversal Bellcore, ETSI, British Telecom and Detector Mercury Systems FSK Demodulator with Data Retiming Computer Telephone Integration High Sensitivity CAS Tone Detection Call Logging Systems Low CAS Tone Falsing in CIDCW Mode Voice-Mail Equipment 1.1 Brief Description The CMX602B is a low power CMOS integrated circuit for the reception of the physical layer signals used in BT s Calling Line Identification Service (CLIP), Bellcore s Calling Identity Delivery System (CID), the Cable Communications Association s Caller Display Services (CDS), and similar evolving systems. It also meets the requirements of emerging Caller Identity with Call Waiting services (CIDCW). The device includes a zero-power ring or line reversal detector, a dual-tone (2130Hz plus 2750Hz) Tone Alert Signal and a 1200-baud FSK V23/Bell202 compatible asynchronous data demodulator with a data retiming circuit which removes the need for a UART in the associated Controller. It is suitable for use in systems to BT specifications SIN227 and SIN242, Bellcore GR-30-CORE and SR-TSV-002476, CCA TW/P&E/312, ETSI ETS 300 659 parts 1 and 2, ETS 300 778 parts 1 and 2 and Mercury Communications MNR 19. 2003 CML Microsystems Plc Calling Line Identifier CMX602B CONTENTS Section Page 1.1 Brief Description ............................................................................... 1 1.2 Block Diagram.................................................................................... 3 1.3 Signal List ............................................................................................ 4 1.4 External Components ..................................................................... 6 1.5 General Description......................................................................... 7 1.5.1 Mode Control Logic ................................................................... 7 1.5.2 Input Signal Amplifier ................................................................ 7 1.5.3 Bandpass Filter .......................................................................... 8 1.5.4 Level Detector ............................................................................ 8 1.5.5 FSK Demodulator....................................................................... 9 1.5.6 FSK Data Retiming..................................................................... 9 1.5.7 Tone Alert Detector.................................................................. 10 1.5.8 Ring or Line Polarity Reversal Detector ................................ 11 1.5.9 Xtal Osc and Clock Dividers ................................................... 13 1.6 Application Notes ........................................................................... 14 1.6.1 On-Hook Operation ................................................................ 14 1.6.2 Off-Hook Operation................................................................ 17 1.7 Performance Specification ......................................................... 19 1.7.1 Electrical Performance ............................................................ 19 1.7.2 Packaging ................................................................................. 23 2003 CML Microsystems Plc 2 D/602B/2