WM8978 w Stereo CODEC with Speaker Driver DESCRIPTION FEATURES Stereo CODEC: The WM8978 is a low power, high quality stereo CODEC DAC SNR 98dB, THD -84dB (A weighted 48kHz) designed for portable applications such as multimedia phone, ADC SNR 95dB, THD -84dB (A weighted 48kHz) digital still camera or digital camcorder. On-chip Headphone Driver with capless option The device integrates preamps for stereo differential mics, and - 40mW per channel into 16 / 3.3V SPKVDD includes drivers for speakers, headphone and differential or 1W output power into 8 BTL speaker / 5V SPKVDD stereo line output. External component requirements are - Capable of driving piezo speakers reduced as no separate microphone or headphone amplifiers - Stereo speaker drive configuration are required. Mic Preamps: Stereo Differential or mono microphone Interfaces Advanced on-chip digital signal processing includes a 5-band - Programmable preamp gain equaliser, a mixed signal Automatic Level Control for the - Psuedo differential inputs with common mode microphone or line input through the ADC as well as a purely rejection digital limiter function for record or playback. Additional digital - Programmable ALC / Noise Gate in ADC path filtering options are available in the ADC path, to cater for Low-noise bias supplied for electret microphones application filtering such as wind noise reduction. Other Features: The WM8978 digital audio interface can operate as a master or Enhanced 3-D function for improved stereo separation a slave. An internal PLL can generate all required audio clocks Digital playback limiter for the CODEC from common reference clock frequencies, such 5-band Equaliser (record or playback) as 12MHz and 13MHz. Programmable ADC High Pass Filter (wind noise reduction) Programmable ADC Notch Filter The WM8978 operates at analogue supply voltages from 2.5V to Aux inputs for stereo analogue input signals or beep 3.3V, although the digital core can operate at voltages down to On-chip PLL supporting 12, 13, 19.2MHz and other clocks 1.71V to save power. The speaker outputs and OUT3/4 line Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and outputs can run from a 5V supply if increased output power is 48kHz sample rates required. Individual sections of the chip can also be powered Low power, low voltage down under software control. - 2.5V to 3.6V (digital: 1.71V to 3.6V) 5x5mm 32-lead QFN package APPLICATIONS Stereo Camcorder or DSC BLOCK DIAGRAM Multimedia Phone Production Data, October 2011, Rev 4.5 WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at WM8978 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ELECTRICAL CHARACTERISTICS ..................................................................... 7 TERMINOLOGY ............................................................................................................ 10 SPEAKER OUTPUT THD VERSUS POWER ...................................................... 11 POWER CONSUMPTION .................................................................................... 12 AUDIO PATHS OVERVIEW ................................................................................ 14 SIGNAL TIMING REQUIREMENTS .................................................................... 15 SYSTEM CLOCK TIMING ............................................................................................. 15 AUDIO INTERFACE TIMING MASTER MODE .......................................................... 15 AUDIO INTERFACE TIMING SLAVE MODE ............................................................. 16 CONTROL INTERFACE TIMING 3-WIRE MODE ...................................................... 17 CONTROL INTERFACE TIMING 2-WIRE MODE ...................................................... 18 INTERNAL POWER ON RESET CIRCUIT .......................................................... 19 DEVICE DESCRIPTION ...................................................................................... 21 INTRODUCTION ........................................................................................................... 21 INPUT SIGNAL PATH ................................................................................................... 23 ANALOGUE TO DIGITAL CONVERTER (ADC) ........................................................... 30 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) ............................................ 36 OUTPUT SIGNAL PATH ............................................................................................... 47 3D STEREO ENHANCEMENT ...................................................................................... 54 ANALOGUE OUTPUTS ................................................................................................. 54 DIGITAL AUDIO INTERFACES ..................................................................................... 70 AUDIO SAMPLE RATES ............................................................................................... 75 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................ 75 LOOPBACK ................................................................................................................... 77 COMPANDING .............................................................................................................. 77 GENERAL PURPOSE INPUT/OUTPUT ........................................................................ 79 OUTPUT SWITCHING (JACK DETECT)....................................................................... 80 CONTROL INTERFACE ................................................................................................ 82 RESETTING THE CHIP ................................................................................................ 83 POWER SUPPLIES ....................................................................................................... 83 RECOMMENDED POWER UP/DOWN SEQUENCE .................................................... 83 POWER MANAGEMENT .............................................................................................. 88 REGISTER MAP .................................................................................................. 89 REGISTER BITS BY ADDRESS ................................................................................... 91 DIGITAL FILTER CHARACTERISTICS ............................................................ 108 TERMINOLOGY .......................................................................................................... 108 DAC FILTER RESPONSES ........................................................................................ 109 ADC FILTER RESPONSES ........................................................................................ 109 HIGHPASS FILTER ..................................................................................................... 110 PD, Rev 4.5, October 2011 w 2