CDB4270

Clocks/Data CDB4270 Evaluation Board for CS4270 Features Description Using the CDB4270 is an excellent way to evaluate the Single-Ended Analog Audio Inputs and Outputs CS4270 CODEC. Other equipment required includes analog/digital audio sources/analyzer, a 5V power sup- ply and a Windows-compatible CS8416 S/PDIF Digital Audio Receiver PC for the GUI. System timing for the IS, Left-Justified or Right-Justi- Header for External Configuration of CS4270 fied audio data formats can be provided by the CS4270, by the CS8416, or by a device connected to the on- Header for External DSP Serial Audio I/O board DSP I/O header. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system 3.3V Logic Interfaces development. RCA jacks are provided for the analog audio inputs and Pre-Defined Software Scripts outputs. Digital S/PDIF transmit or receive data I/O is available via either RCA jacks or optical connectors. Demonstrates Recommended Layout The Windows GUI software provided allows for easy configuration of the CDB4270. The GUI software com- municates with the board via USB or serial port Windows -Compatible GUI Interface for Board connections to configure the CS4270 registers. Configuration and Control ORDERING INFORMATION CDB4270 Evaluation Board Hardware Serial/USB Control Port Setup CS8406 S/PDIF 2 ANALOG INPUT I C/SPI Header Output Single-Ended Input MCLK BUS CS4270 ADC/DAC Clocks/ ANALOG OUTPUT Data CS8416 Hardware S/PDIF Setup Hardware Single-Ended Input Setup FPGA Clocks Output /Data HW Setup Switches Osc. DSP HEADER Copyright Cirrus Logic, Inc. 2006 SEPTEMBER 06 (All Rights Reserved) CDB4270 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 5 1.1 Power ............................................................................................................................................... 5 1.2 Grounding and Power Supply Decoupling ........................................................................................ 5 1.3 FPGA ................................................................................................................................................ 5 1.4 CS4270 Audio CODEC .................................................................................................................... 5 1.5 CS8406 Digital Audio Transmitter .................................................................................................... 5 1.6 CS8416 Digital Audio Receiver ........................................................................................................ 5 1.7 Canned Oscillator ............................................................................................................................. 6 1.8 External Control Headers ................................................................................................................. 6 1.9 Analog Input ..................................................................................................................................... 6 1.10 Analog Outputs ............................................................................................................................... 8 1.11 Control Port .................................................................................................................................... 8 1.12 Hardware Mode Switches ............................................................................................................... 8 2. FPGA OVERVIEW .................................................................................................................................. 9 2.1 FPGA Architecture ............................................................................................................................ 9 2.2 Internal Sub-Clock Routing ............................................................................................................... 9 2.3 Internal Data Routing ...................................................................................................................... 10 2.4 Internal Drivers ............................................................................................................................... 11 2.5 External MCLK Control ................................................................................................................... 12 3. SOFTWARE MODE .............................................................................................................................. 13 3.1 CDB4270 Control Scripts ............................................................................................................... 13 3.1.1 S/PDIF In, Analog Out ........................................................................................................... 13 3.1.2 Analog In, S/PDIF Out ........................................................................................................... 13 3.1.3 Analog In, Analog Out (Digital Loop-Back) ............................................................................ 13 3.1.4 DSP In, Analog Out ............................................................................................................... 13 3.2 CDB4270 GUI ................................................................................................................................. 14 3.3 Register Maps Control Tabs ........................................................................................................... 15 4. HARDWARE MODE ............................................................................................................................. 18 5. FPGA GUI REGISTER DESCRIPTION ................................................................................................ 18 5.1 FPGA REGISTER QUICK REFERENCE ....................................................................................... 18 5.2.1 Revision Number Bits (Bits 7:0) ............................................................................................ 19 5.3.1 SDOUT Routing to Header (Bits 7:6) .................................................................................... 20 5.3.2 MCLK Source (Bit 4) ............................................................................................................. 20 5.3.3 SDOUT Routing to DUT (Bits 3:2) ......................................................................................... 20 5.3.4 Subclock Routing (Bits 1:0) ................................................................................................... 21 5.4.1 CS8406 OMCLK Divider Control (Bits 7:6) ........................................................................... 21 5.4.2 CS8406 Master/Slave Select (Bit 4) ...................................................................................... 22 5.4.3 CS8406 SDIN Format Select (Bit 3) ...................................................................................... 22 5.4.4 CS8406 SDIN Source (Bits 1:0) ............................................................................................22 5.5.1 CS8416 RMCLK Divider Control (Bit 6) ................................................................................ 23 5.5.2 CS8416 Master/Slave Select (Bit 4) ...................................................................................... 23 5.5.3 CS8416 SDOUT Format Select (Bit 3) .................................................................................. 23 6. CDB4270 HARDWARE MODE SETTINGS ......................................................................................... 24 7. CDB CONNECTORS, SWITCHES, INDICATORS AND JUMPERS ................................................... 26 8. ADC PERFORMANCE PLOTS ............................................................................................................ 27 9. DAC PERFORMANCE PLOTS ............................................................................................................ 31 10. CDB BLOCK DIAGRAM ................................................................................................................ 36 11. CDB SCHEMATICS ............................................................................................................................ 37 12. CDB LAYOUT ..................................................................................................................................... 46 13. CHANGES MADE TO REV. B BOARD ............................................................................................. 49 13.1 Modifications (Done by Cirrus Logic) .......................................................................................... 49 14. REVISION HISTORY .......................................................................................................................... 50 2 DS686DB3