CDB4245

CDB4245 Evaluation Board for CS4245 Features Description The CDB4245 evaluation board is an excellent means z Single-ended Analog Inputs for evaluating the CS4245 CODEC. Evaluation requires z Single-ended Analog Outputs an analog/digital signal source and analyzer, and power z CS8406 S/PDIF Digital Audio Transmitter supplies. A Windows PC compatible computer must be used to evaluate the CS4245. z CS8416 S/PDIF Digital Audio Receiver System timing for the IS, Left-Justified and Right-Justi- z Independent ADC and DAC Clock Domains fied interface formats can be provided by the CS4245, z Header for Optional External Software the CS8416, the CS8406, or by a PCM I/O stake header Configuration of CS4245 with an external source connected. z Header for External PCM Serial Audio I/O RCA phono jacks are provided for the CS4245 analog in- puts and outputs. Digital data I/O is available via RCA z 3.3 V Logic Interface phono or optical connectors to the CS8416 and CS8406. z Pre-defined Software Scripts The Windows software provides a GUI to make config- z Demonstrates Recommended Layout and uration of the CDB4245 easy. The software Grounding Arrangements communicates through the PCs serial port to configure the control port registers so that all features of the z Windows Compatible Software Interface CS4245 can be evaluated. The evaluation board may to Configure CS4245 and Inter-board also be configured to accept external timing and data Connections signals for operation in a user application during system development. ORDERING INFORMATION CDB4245 Evaluation Board I Passive Input Filter Passive Output Filter M Active Input Filter U Active Output Filter X Microphone Input Test Points CS4245 Master Clock Master Clock Canned Canned Oscillator Oscillator Header Header Control Port Interface CS8416 CS8406 CS8416 CS8406 FPGA Sub-clocks and Data Cirrus Logic, Inc. Copyright Cirrus Logic, Inc. 2005 www.cirrus.com FEB 05 (All Rights Reserved) DS656DB1CDB4245 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................... 4 1.1 Power ................................................................................................................................. 4 1.2 Grounding and Power Supply Decoupling ......................................................................... 4 1.3 CS4245 Audio CODEC ...................................................................................................... 4 1.4 CS8406 Digital Audio Transmitter ...................................................................................... 4 1.5 CS8416 Digital Audio Receiver .......................................................................................... 4 1.6 FPGA ................................................................................................................................. 5 1.7 Canned Oscillators ............................................................................................................. 5 1.8 External Control Headers ...................................................................................................5 1.9 Analog Inputs ..................................................................................................................... 5 1.10 Analog Outputs ................................................................................................................ 5 1.10.1 DAC Outputs ....................................................................................................... 5 1.10.2 Auxiliary Outputs ................................................................................................. 5 1.11 Serial Control Port ............................................................................................................ 5 1.12 USB Control Port ............................................................................................................. 6 2. SYSTEM CLOCKING ............................................................................................................... 6 2.1 Clock Domain 1 .................................................................................................................. 6 2.2 Clock Domain 2 .................................................................................................................. 6 3. SYSTEM DATA ROUTING ....................................................................................................... 6 3.1 CS4245 SDIN Source ........................................................................................................ 6 3.2 CS8406 SDIN Source ........................................................................................................ 6 4. PC SOFTWARE CONTROL ..................................................................................................... 7 4.1 CDB4245 Controls Tab ...................................................................................................... 7 4.2 S/PDIF I/O Controls Tab ....................................................................................................8 4.3 Register Maps Tab ............................................................................................................. 9 4.4 Pre-Configured Script Files ................................................................................................9 4.4.1 Oscillator Clock - ADC Ch 1 to DAC & SPDIF Out ............................................... 9 4.4.2 SPDIF Recovered Clock - SPDIF to DAC & ADC to SPDIF ............................... 10 5. FPGA REGISTER QUICK REFERENCE ............................................................................... 11 6. FPGA REGISTER DESCRIPTION ......................................................................................... 12 7. CDB CONNECTORS, JUMPERS, AND SWITCHES ............................................................. 15 8. CDB BLOCK DIAGRAM ..................................................................................................... 17 9. CDB SCHEMATICS ............................................................................................................... 18 10. CDB LAYOUT ...................................................................................................................... 26 11. REVISION HISTORY ............................................................................................................ 29 2 DS656DB1