Product Information

BCM8705LBIFBG

BCM8705LBIFBG electronic component of Broadcom

Datasheet
Broadcom Limited 10GbE/10GFC XAUI to XFI LANPHY

Manufacturer: Broadcom
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

32: USD 151.0757 ea
Line Total: USD 4834.42

0 - Global Stock
MOQ: 32  Multiples: 32
Pack Size: 32
Availability Price Quantity
0 - WHS 1


Ships to you between Tue. 14 May to Mon. 20 May

MOQ : 32
Multiples : 32

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BCM8705LBIFBG
Broadcom

32 : USD 151.0757
34 : USD 149.065
66 : USD 145.3308
160 : USD 141.7403
320 : USD 138.2933

     
Manufacturer
Product Category
RoHS - XON
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BCM8705 SERIAL 10-GBE/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND XAUI INTERFACE FEATURES SUMMARY OF BENEFITS Fully integrated CMU, CDR, SerDes, limiting amplifier, Best performance for LAN (10-GbE) and WAN (OC-192 EyeOpener , and 4-lane XAUI interface SONET) application PMD interface supported serial rates: 9.953/10.3125/ 10.5188-Gbps Universal design for 10-GbE, SONET, and 10 GFC for Receive equalization on XAUI and 10G serial interfaces XENPAK/X2 module Transmit pre-emphasis and amplitude control on XAUI interface Compliant to XENPAK/X2 3.0 and XPAK MSA optical 10G PMD interface phase and decision threshold adjust module standards WIS layer for EOS/WAN applications Integrated and compact design allows for high-density line card applications SONET performance monitoring Supports Broadcoms StrataXGS Ethernet switches service Upgrade path for existing Broadcom LAN PHY transceivers aware flow control (SAFC) protocol Build-in features reduce external components Meets and exceeds industry standard Clean-up PLL IEEE 802.3ae serial Ethernet transceiver (LAN/WAN PHY), 2.5V voltage regulator output MDIO Clause 45 management interface with extended indirect In-rush current limits address register access 10-Gigabit Fibre Channel draft, rev 3.0 Support for XFP/XFI interfaces Support for XENPAK/X2 3.0 and XPAK MSA optical module standards APPLICATIONS Additional features Jumbo packets support in WAN mode XENPAK, X2, XPAK modules Reference clock output for XFP module reference clock 2 I C master to control XFP module from device Interface to XFP modules Staged power-up mode to minimize in-rush current Loopback modes supporting IEEE standards modes LAN/MAN/WAN switch/routers Built-in self-test (BIST) and PRBS generator/checker Hubs and repeaters Pin-compatible with the BCM8704 Network interface cards (NICs) Low power: LAN mode 900 mW, WAN mode 1.0W to 1.1W Available in 13-mm x 13-mm and 17-mm x 17-mm plastic BGA (Pb-free version also available) BCM8705 Block Diagram XAUI BCM8705 OTX 9.953/10.3125/10.5188 RS Gbps Media Access ORX MAC Controller Interface Optical PMD MDC MDIO Management Interface EEPROM XGXS XGXS PCS/PMA WISOVERVIEW System/MAC Interface Line/Fiber-Optic Module Interface XAUI Differential CML X[A:D]OP/N outputs AC-coupled 10G Serial internally biased AC-coupled PDIP/N XAUI Inputs X[A:D]IP/N differential CML internally biased inputs differential CML PPDOUT PCOP/N 10G Serial XPDOUT Differential CML Outputs External VCXO PDOP/N PEXTCLKP/N AC-coupled XEXTCLKP/N internally biased PVCOXP/N differential LVPECL SYSRSTB RSTB MDC MDIO VCPCDR CDR Loop PMD Analog PRTAD[4:0] VCNCDR Filter CMOS Control PLOSB/A1 and XAUI PMD Status PCDRLK OPTXENB0/1 PCMULK OPTXRST0/1 REFCLKOUT OPRXLOS Optics OPBIASFLT Control 2WENB OPTMPFLT and CONFIG[1:0] CMOS OPPWFLT Status OPTXFLT LASI OPRXFLT TXONOFF OPOUTLVL SDA OPINLVL 2-Wire CMOS SCL interface TRSTB JTCK JTAG TMS TDI TDO BCM8705 Fully Integrated Interface The BCM8705 Ethernet/Fibre Channel/SONET LAN/WAN PHY is a On-chip clock synthesis is performed by the high-frequency low-jitter fully integrated serialization/deserialization (9.953/10.3125/ phase-locked loops for the PMD and XAUI output retimers. Individual 10.5188-Gbps) interface device performing the extension functions for a PMD and XAUI clock recovery is performed on the device by 10-gigabit serial Ethernet reconciliation sublayer (RS) interface. The synchronizing directly to their respective incoming data streams. Elastic XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B buffers are provided to allow the XAUI and PMD interfaces to operate coding, SerDes, WIS, clock multiplication unit (CMU), and clock and in asynchronous configuration. Only an external 155.52/156.25/ data recovery (CDR). 159.38-MHz oscillator is required for the reference clock input. For WAN applications, a WIS-compliant framer with flexible clocking The BCM8705 is available in a 13-mm 13-mm, 256-pin FBGA with a modes allows transmission of Ethernet traffic over a WAN network. 0.8-mm ball pitch and also in a 17-mm x 17-mm, 256-pin 1-mm ball pitch RoHS-compliant package. Broadcom , the pulse logo, Connecting everything , the Connecting everything logo, EyeOpener , and StrataXGS are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. BROADCOM CORPORATION Phone: 949-450-8700 16215 Alton Parkway, P.O. Box 57013 Fax: 949-450-8710 Irvine, California 92619-7013 E-mail: info@broadcom.com Web: www.broadcom.com 2006 by BROADCOM CORPORATION. All rights reserved. 8705-PB02-R 04/17/06

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
 AVAGO TECHNOLOGIES
AV4
AV9
Avago
AVAGO TECHNOLOGIES
Avago Technologies US Inc.
AVAGO(Broadcom)
Broadcom Avago
BROADCOM (AVAGO)
Broadcom / Avago
BROADCOM CORPORATION
Broadcom Limited
PLX Technology Avago
PLX Technology / Avago

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