APS512XXN-OBR-BG

APS256XXN-OBRx DDR Octal SPI PSRAM Double-Data-Rate Octal SPI PSRAM Specifications Features Single Supply Voltage: Low Power Features: o V =1.62 to 1.98V o Partial Array Self-Refresh (PASR) DD o V =1.62 to 1.98V o Auto Temperature Compensated Self- DDQ Refresh (ATCSR) self-managed by a built-in Interface: Octal SPI with DDR mode, temperature sensor o Two bytes transfer per clock X8 o Two words transfer per clock X16 o Ultra Low Power Half Sleep mode with data o Mode register configurable X8(default)/X16 retention. o Note: 1 Word = 2 Bytes in this document. Software reset Performance: Clock rate up to 200MHz, Reset pin available 400MBps read/write throughput X8 Output driver LVCMOS with programmable 800MBps read/write throughput X16 drive strength Organization: 256Mb in X8 mode (default) Data mask (DM) for write operation o 32M x 8bits with 2048 bytes per page Data strobe (DQS) for high speed read operation o Column address: AY0 to AY10 Register configurable write and read latencies o Row address: AX0 to AX13 Write burst length Organization: 256M in X16 mode o max 2048 Bytes in X8/1024 Words in X16 o 16M x 16bits with 1024 Words per page o min 2 Bytes in X8 /2 Words in X16 o Column address: AY0 to AY9 Wrap & hybrid burst in o Row address: AX0 to AX13 o 16/32/64/128/2K Bytes length in X8 mode. Refresh: Self-managed o 16/32/64/128/1K Words length in X16 Operating temperature range mode. o TC = -40C to +85C (standard range)* Linear Burst Commands o TC = -40C to +105C (extended range)* Row Boundary Crossing (RBX) read operations Typical mean Room Standby Current: enabled via Mode Register o 90A 25C (Standby mode) X16 mode can be configured by setting o 40A 25C (Half Sleep Mode with data MR8 6 =1 (default is X8 mode and MR8 6 =0) retained) Maximum Standby Current: o 1100A 105C o 680A 85C * please refer to Table 1 APM Octal PSRAM Datasheet.pdf - Rev. 1.00 Jul 24, 2020 1 of 30 AP Memory reserves the right to change products and/or specifications without notice 2020 AP Memory. All rights reserved APS256XXN-OBRx DDR Octal SPI PSRAM Table of Contents 1 Table of Contents 1 Table of Contents ............................................................................................................. 2 2 Package Information ........................................................................................................ 4 2.1 Package Types : BGA 24b X8/X16 (BG) ................................................................... 4 2.2 Package Outline Drawing ........................................................................................ 5 2.2.1 BGA 24b , package code BG .................................................................................. 5 3 Ordering Information ....................................................................................................... 6 4 Signal Table ...................................................................................................................... 7 5 Power-Up Initialization .................................................................................................... 8 5.1 Power-Up Initialization Method 1 (via. RESET pin) ............................................... 8 5.2 Power-Up Initialization Method 2 (via. Global Reset) ............................................ 9 6 Interface Description ..................................................................................................... 10 6.1 Address Space ....................................................................................................... 10 6.2 Burst Type & Length .............................................................................................. 10 6.3 Command/Address Latching ................................................................................. 10 6.4 Command Truth Table .......................................................................................... 10 6.5 Read Operation ..................................................................................................... 11 6.6 Write Operation .................................................................................................... 14 6.7 Control Registers ................................................................................................... 15 6.8 Half Sleep Mode .................................................................................................... 22 6.9 Deep Power Down Mode ...................................................................................... 23 7 Electrical Specifications: ................................................................................................ 24 7.1 Absolute Maximum Ratings .................................................................................. 24 7.2 Pin Capacitance ..................................................................................................... 24 7.3 Decoupling Capacitor Requirement ...................................................................... 25 7.3.1 Low ESR cap C1: ................................................................................................... 25 7.3.2 Large cap C2: ....................................................................................................... 25 7.4 Operating Conditions ............................................................................................ 25 7.5 DC Characteristics ................................................................................................. 26 7.6 ISB Partial Array Refresh Current .......................................................................... 27 APM Octal PSRAM Datasheet.pdf - Rev. 1.00 Jul 24, 2020 2 of 30 AP Memory reserves the right to change products and/or specifications without notice 2020 AP Memory. All rights reserved