EVALUATION KIT AVAILABLE Click here for production status of specific part numbers. MAX5855 16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface General Description Benefits and Features The MAX5855 high-performance, interpolating and modu- Simplifies RF Design and Enables New lating, 16-bit, 4.9Gsps RF DAC can directly synthesize up Communication Architectures to 1000MHz of instantaneous bandwidth from DC to fre- Eliminates I/Q Imbalance and LO Feedthrough quencies greater than 2.45GHz. The device is optimized Enables Multi-Band RF Modulation for cable access and digital video broadcast applications Direct RF Synthesis of 1GHz Bandwidth and meets spectral emission requirements for a broad 4.9152Gsps DAC Output Update Rate set of radio transmitters and modulators including DOC- High-Performance 14-Bit RF DAC Core SIS 3.1/3.0, DVB-C/C2, DVB-T2, DVB-S2X, ISDB-T, and Digital Baseband I/Q with 4x Interpolation EPoC. Digital Quadrature Modulator + NCO for Full Agility The device integrates interpolation filters, a digital quadra- Sub-1Hz NCO Resolution ture modulator, a numerically controlled oscillator (NCO), Integrated Clock Multiplying PLL + VCO clock multiplying PLL + VCO and a 14-bit RF DAC core. Flexible and Configurable The 4x linear phase interpolation filter simplifies recon- 5-Lane JESD204B Input Data Interface struction filtering, while enhancing passband dynamic per- Subclass-0 Compliant formance, and reducing the input data bandwidth required 9.8304Gbps Per Lane from an FPGA. The NCO allows for fully agile modulation Divided Reference Clock Output of the input baseband signal for direct RF synthesis. SPI Interface for Device Configuration The MAX5855 input interface accepts 16-bit input data by Ordering Information appears at end of data sheet. way of a five-lane, JESD204B SerDes data input inter- face that is Subclass-0 compliant and operates at a data rate of 9.8304Gbps. The MAX5855 clock input has a flexible interface that ac- cepts a differential sine-wave or square-wave reference input clock signal at 245.75MHz, 491.52MHz, or 983.04MHz. A clock multiplying PLL and VCO is used to internally generate the 4.9152GHz sampling clock from the reference clock. The device provides a divided refer- ence clock output to ensure synchronization between the data source and the DAC. The integrated RF DAC uses a differential current-steering architecture that includes a differential 50 internal termi- nation and can produce a 3dBm full-scale output signal level on a 50 external load. Operating from 1.0V and 1.8V power supplies, the device consumes 2.7W at 4.9Gsps. The device is offered in a compact 144-pin, 10mm x 10mm, FCCSP package and is specified for the extended industrial temperature range (-40C to +85C). Applications DOCSIS 3.1/3.0 Remote PHY and CCAP Digital Video Broadcast Modulators DVB-C/C2/DVB-T2/DVB-S2X/ISDB-T Ethernet PON Over Coax (EPoC) Point-to-Point Wireless Instrumentation 19-100312 Rev 1 4/19MAX5855 16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface Simplified Block Diagram PLL COMP V COBYP MAX5855 CLKP CLOCK RCLKP PLL N CLKN DISTRIBUTION RCLKN 16 5 MUTE DP 4:0 4 DN 4:0 14-BIT 14 OUTP JESD 4.9Gsps 204B OUTN RF DAC SYNCNP 16 SYNCNN 4 MOD INTB Reference Quadrature REFERENCE QUADRATURE SPI PORT SPI Port SYSTEM NCO System NCO RESETB www.maximintegrated.com Maxim Integrated 2 V DD AVDD AVCLK GND CSBP REFIO FSADJ DACREF CSB SCLK SDI SDO