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EVAL-ADUM4121-1EBZ

EVAL-ADUM4121-1EBZ electronic component of Analog Devices

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Power Management IC Development Tools Eval board for ADUM4121

Manufacturer: Analog Devices
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1: USD 71.7912 ea
Line Total: USD 71.79

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EVAL-ADUM4121-1EBZ
Analog Devices

1 : USD 91.5648

     
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High Voltage, Isolated Gate Driver with Internal Miller Clamp, 2 A Output Data Sheet ADuM4121/ADuM4121-1 FEATURES GENERAL DESCRIPTION 1 2 A peak output current (<2 R ) The ADuM4121/ADuM4121-1 are 2 A isolated, single-channel DSON 2.5 V to 6.5 V input drivers that employ Analog Devices, Inc.s iCoupler technology 4.5 V to 35 V output to provide precision isolation. The ADuM4121/ADuM4121-1 Undervoltage lockout (UVLO) at 2.5 V V DD1 provide 5 kV rms isolation in the wide-body, 8-lead SOIC package. Multiple UVLO options on V DD2 Combining high speed CMOS and monolithic transformer Grade A: 4.4 V (typical) UVLO on V DD2 technology, these isolation components provide outstanding Grade B: 7.3 V (typical) UVLO on V DD2 performance characteristics superior to alternatives such as the Grade C: 11.3 V (typical) UVLO on V DD2 combination of pulse transformers and gate drivers. Precise timing characteristics The ADuM4121/ADuM4121-1 operate with an input supply 53 ns maximum isolator and driver propagation delay ranging from 2.5 V to 6.5 V, providing compatibility with lower CMOS input logic levels voltage systems. In comparison to gate drivers that employ high High common-mode transient immunity: >150 kV/s voltage level translation methodologies, the ADuM4121/ High junction temperature operation: 125C ADuM4121-1 offer the benefit of true, galvanic isolation Default low output between the input and the output. Internal Miller clamp The ADuM4121/ADuM4121-1 include an internal Miller clamp Safety and regulatory approvals (pending) that activates at 2 V on the falling edge of the gate drive output, UL recognition per UL 1577 supplying the driven gate with a lower impedance path to reduce 5 kV rms for 1-minute withstand the chance of Miller capacitance induced turn on. CSA Component Acceptance Notice 5A VDE certificate of conformity (pending) Options exists to allow the thermal shutdown to be enabled or DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 disabled. As a result, the ADuM4121/ADuM4121-1 provide V = 849 V peak IORM reliable control over the switching characteristics of insulated Wide-body, 8-lead SOIC gate bipolar transistor (IGBT)/metal oxide semiconductor field, effect transistor (MOSFET) configurations over a wide range of APPLICATIONS switching voltages. Switching power supplies Isolated IGBT/MOSFET gate drives Industrial inverters Gallium nitride (GaN)/silicon carbide (SiC) power devices FUNCTIONAL BLOCK DIAGRAM UVLO TSD ADuM4121/ 1 8 V V DD1 DD2 ADuM4121-1 DECODE AND 2 ENCODE 7 V V + OUT I LOGIC V I 3 6 CLAMP 2V 4 5 GND GND 1 UVLO 2 Figure 1. 1 Protected by U.S. Patents 5,952,849 6,873,065 7,075,239. Other patents pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 14967-001ADuM4121/ADuM4121-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................7 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Applications Information .............................................................. 12 Specifications ..................................................................................... 3 Printed Circuit Board (PCB) Layout ....................................... 12 Electrical Characteristics ............................................................. 3 Propagation Delay-Related Parameters ................................... 12 Regulatory Information ............................................................... 4 Undervoltage Lockout ............................................................... 12 Package Characteristics ............................................................... 4 Output Load Characteristics ..................................................... 13 Insulation and Safety-Related Specifications ............................ 5 Power Dissipation....................................................................... 13 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Insulation Lifetime ..................................................................... 14 Characteristics .............................................................................. 5 Typical Applications ................................................................... 14 Recommended Operating Conditions ...................................... 5 Outline Dimensions ....................................................................... 16 Absolute Maximum Ratings ............................................................ 6 Ordering Guide .......................................................................... 16 REVISION HISTORY 10/2016Revision 0: Initial Version Rev. 0 Page 2 of 16

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