DEMO MANUAL DC1717A LTC4417 Prioritized PowerPath Controller Description Demonstration circuit DC1717A uses the LTC 4417 to enabled and powers the load. Two or more LTC4417s arbitrate between three input supply rails, selecting the can be cascaded to provide switchover between more highest priority, valid supply to power the load. The rails than three rails. priority is defined by the input connection (V1-V3). Each Design files for this circuit board are available at rail has overvoltage and undervoltage thresholds set by DEMO MANUAL DC1717A o The LTC4417 controls three sets of external back-to-back has the highest priority, V3 has the lowest. The highest P-channel MOSFETs to connect the proper rail to the priority input that is also within its valid range is selected load. Precision comparators are used to monitor each of to power the output. V1, V2 and V3 inputs are protected the three input rails for both UV and OV conditions. The against input glitches of up to 42V. Maximum load cur- highest priority input supply whose voltage is within its rent is 2A, limited by MOSFET capability. respective OV/UV window for at least 256ms is consid- Logic and LEDs are included to provide visual information ered valid and connected to the load. Low signals on the about the operating status. These circuits are powered VALID1, VALID2, and VALID3 pins indicate validation of from a 6V to 24V auxiliary voltage input (AVI) which is the V1, V2, and V3 voltages. regulated by an LT3060 (U4) to 5V. This auxiliary 5V rail DC1717A is designed to operate from inputs of 12V, also powers 100k pull-ups for VALID pins. AVI must be 5V, and 8V, applied to V1, V2 and V3 respectively. The present in order for the board to operate. See the Modifica- valid range of each supply is 20%, as set by OV and UV tion section for a means of eliminating AVI. comparators and their associated resistive dividers. V1 o p To eliminate back-and-forth switching during rail switcho- in a low current state and resetting the 256ms timers ver, the LTC4417 provides a 30mV hysteresis in the OV and used to validate input rail voltages. It requires at least UV comparators, and an externally adjustable current mode 256ms to validate each rail voltage after the SHDN pin hysteresis using the OV/UV resistive dividers. DC1717As signal goes high. input reference hysteresis is 6%, and can be changed to The LTC4417 features two different driving modes for the 3% by moving the JP1 jumper to the 30mV position. P-channel MOSFET gates. The controllers break-before-make switching method One mode is provided by the internal soft-start circuitry, prevents cross conduction between input channels and which limits output voltage slew rate to no more than reverse current from the output capacitor into the selected 5V/ms. As the highest output voltage slew rate, usually, can input supply. impose the highest requirements for circuit components, Each channels control circuit of the LTC4417 has a REV 5V/ms should be taken into account as a worst case for comparator, which monitors the connecting input supply component selection. and output load voltage. The REV comparator delays the The soft-start circuitry is enabled each time under the connection until the output voltage droops 120mV below following conditions: the input voltage. This prevents reverse current. If the LTC4417 is first powered on, or The LTC4417 has two common control pins: EN and SHDN. If SHDN is forced low, or Pulling the EN pin below 1V turns off all external back-to- If V falls below ~0.7V back P-channel MOSFETs. When this pin is driven above OUT 1V, the highest priority valid channel is connected to the Soft-start is disabled when: load. All these actions are provided without resetting the any channel turns off, including the channel that is soft 256ms OV/UV timers. starting. Pulling the SHDN pin below 0.8V turns off all external 32ms validation delay time has elapsed during the soft- back-to-back P-channel MOSFETs, placing the controller start interval. dc1717afa 2 rinciples perating verview