DEMO MANUAL DC1500A LTC2393-16/LTC2392-16/ LTC2391-16: 16-Bit,1Msps/ 0.5Msps/0.25Msps Low Noise ADCs DESCRIPTION The LTC 2393/LTC2392/LTC2391-16 are low noise high performance of the LTC2393-16 in both parallel and serial speed ADCs with both parallel and serial outputs that modes and is intended to demonstrate recommended can operate from a single 5V supply. The following text grounding, component placement and selection, routing refers to the LTC2393-16 but applies to all three parts. and bypassing for this ADC. Also several suggested driver The only difference being the maximum sample rates. The circuits for the analog inputs will be presented. LTC2393-16 supports a large 4.096V fully differential input Design les for this circuit board are available at www. range. This makes it ideal for high performance applica- linear.com/demo. tions that require maximum dynamic range. Demonstration L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. circuit 1500A provides the user a means of evaluating the 9V GND 9V CLK IN 1MHz MAX (80MHz FOR SERIAL) 3.3V MAX P-P A IN 0V TO 4.096V MAX (NOT NEEDED UNLESS U2 IS DISABLED) TO DC718 + A IN 0V TO 4.096V MAX dc1500a F01 Figure 1. DC1500A Connection Diagram Table 1 MAX PARALLEL CLK IN MAX SERIAL CLK IN ASSEMBLY VERSION PART NUMBER MAX CONVERSION RATE FREQUENCY FREQUENCY DC1500A-A LTC2393CLX-16 1Msps 1MHz 80MHz DC1500A-B LTC2392CLX-16 0.5Msps 500kHz 40MHz DC1500A-C LTC2391CLX-16 0.25Msps 250kHz 20MHz dc1500af 1DEMO MANUAL DC1500A QUICK START PROCEDURE Check to make sure that all switches and jumpers are Run the QuickEval-II software (Pscope.exe version K66 set as shown in the connection diagram of Figure 1. The or later) supplied with DC718B/C or download it from default connections con gure the ADC for parallel op- www.linear.com. eration with the output data in offset binary format. The Complete software documentation is available from the analog input is AC-coupled and the internal reference of Help menu. Updates can be downloaded from the Tools the ADC is used. menu. Check for updates periodically as new features Connect DC1500A to a DC718B/C USB High Speed Data may be added. Collection Board using connector J1. Connect DC718B/C The Pscope software should recognize DC1500A and to a host PC with a standard USB A/B cable. Apply 9V con gure itself automatically. to the indicated terminals. Apply a low jitter signal source + Click the Collect button (see Figure 6) to begin acquiring to J3 (AIN ). The default setup uses a single ended to dif- data. The Collect button then changes to Pause, which ferential converter so that it is only necessary to apply an can be clicked to stop data acquisition. input signal to J3. Connect a low jitter 1MHz 3.3V sine P-P wave or square wave to connector J2 (CLK). Note that J2 has a 50 termination resistor to ground. SETUP be removed. Slow rising edges may compromise SNR of DC Power the converter in the presence of high amplitude higher DC1500A requires 9VDC at approximately 100mA. Most frequency input signals. of the supply current is consumed by the CPLD, op amps, regulators and discreet logic on the board. The 9VDC Data Output input voltage powers the ADC through LT1763 regulators Parallel data output from this board (0V to 3.3V default), which provide protection against accidental reverse bias. if not connected to DC718, can be acquired by a logic Additional regulators provide power for the CPLD and op analyzer, and subsequently imported into a spreadsheet, or amps. See Figure 1 for connection details. mathematical package depending on what form of digital signal processing is desired. Alternatively, the data can be Clock Source fed directly into an application circuit. Use pin 3 of J1 to You must provide a low jitter 3.3V sine or square wave P-P latch the data. The data can be latched using either edge to J2. The clock input is AC-coupled so the DC level of the of this signal. The data output signal levels at J1 can also clock signal is not important. A generator like the HP8644 be reduced to 0V to 2.5V if the application circuit cannot or similar is recommended. Even a good generator can start tolerate the higher voltage. This is accomplished by moving to produce noticeable jitter at low frequencies. Therefore JP7 to the 2.5V position. it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate. One Reference way to do this is by placing the ADC in the serial mode. JP4, JP5 and JP6 allow you to select an on chip refer- This can be accomplished by setting the SER/PARL posi- ence or an external LT1790A-4.096 as the reference. The tion of SW1 to the high position. In the serial mode the worst case initial accuracy and drift speci cations of the ratio of clock frequency to conversion rate is 80:1. In external reference are better than the on chip reference. the parallel mode there is a 1:1 ratio of clock frequency To use the internal reference set JP6 to FLT, JP4 to ADC to conversion rate. If the clock input is to be driven with and JP5 to REFIN. To use the LT1790A-4.096 set JP5 and logic, it is recommended that the 50 terminator (R17) JP6 to GND and JP4 to EXT. dc1500af 2