ADSP-BF531SBSTZ400

Blackfin Embedded Processor ADSP-BF531/ADSP-BF532/ADSP-BF533 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor Parallel peripheral interface PPI, supporting ITU-R 656 video data formats Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter 2 dual-channel, full duplex synchronous serial ports, sup- 2 porting eight stereo I S channels RISC-like register and instruction model for ease of pro- gramming and compiler-friendly support 2 memory-to-memory DMAs Advanced debug, trace, and performance monitoring 8 peripheral DMAs Wide range of operating voltages (see Operating Conditions SPI-compatible port on Page 20) Three 32-bit timer/counters with PWM support Qualified for Automotive Applications (see Automotive Prod- Real-time clock and watchdog timer ucts on Page 62) 32-bit core timer Programmable on-chip voltage regulator Up to 16 general-purpose I/O pins (GPIO) 160-ball CSP BGA, 169-ball PBGA, and 176-lead LQFP UART with support for IrDA packages Event handler Debug/JTAG interface MEMORY On-chip PLL capable of frequency multiplication Up to 148K bytes of on-chip memory (see Table 1 on Page 3) Memory management unit providing memory protection External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI and external memory JTAG TEST AND EMULATION VOLTAGE REGULATOR INTERRUPT WATCHDOG CONTROLLER TIMER B RTC L1 L1 DMA PPI INSTRUCTION DATA CONTROLLER MEMORY MEMORY GPIO TIMER0-2 PORT F DMA EXTERNAL SPI DMA CORE BUS BUS EXTERNAL ACCESS BUS UART EXTERNAL PORT FLASH, SDRAM CONTROL SPORT0-1 16 BOOT ROM Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com DMA ACCESS BUS PERIPHERAL ACCESS BUSADSP-BF531/ADSP-BF532/ADSP-BF533 TABLE OF CONTENTS Features ................................................................. 1 Development Tools .............................................. 15 Memory ................................................................ 1 Additional Information ........................................ 16 Peripherals ............................................................. 1 Related Signal Chains ........................................... 16 General Description ................................................. 3 Pin Descriptions .................................................... 17 Portable Low Power Architecture ............................. 3 Specifications ........................................................ 20 System Integration ................................................ 3 Operating Conditions ........................................... 20 Processor Peripherals ............................................. 3 Electrical Characteristics ....................................... 22 Blackfin Processor Core .......................................... 4 Absolute Maximum Ratings ................................... 25 Memory Architecture ............................................ 4 ESD Sensitivity ................................................... 25 DMA Controllers .................................................. 8 Package Information ............................................ 26 Real-Time Clock ................................................... 8 Timing Specifications ........................................... 27 Watchdog Timer .................................................. 9 Output Drive Currents ......................................... 43 Timers ............................................................... 9 Test Conditions .................................................. 45 Serial Ports (SPORTs) ............................................ 9 Thermal Characteristics ........................................ 49 Serial Peripheral Interface (SPI) Port ....................... 10 160-Ball CSP BGA Ball Assignment ........................... 50 UART Port ........................................................ 10 169-Ball PBGA Ball Assignment ................................. 53 General-Purpose I/O Port F ................................... 10 176-Lead LQFP Pinout ............................................ 56 Parallel Peripheral Interface ................................... 11 Outline Dimensions ................................................ 58 Dynamic Power Management ................................ 11 Surface-Mount Design .......................................... 61 Voltage Regulation .............................................. 13 Automotive Products .............................................. 62 Clock Signals ..................................................... 13 Ordering Guide ..................................................... 63 Booting Modes ................................................... 14 Instruction Set Description ................................... 15 REVISION HISTORY 8/13 Rev. H to Rev. I Updated Development Tools .................................... 15 Corrected Conditions value of the V specification in IL Operating Conditions ............................................. 20 Added notes to Table 30 in Serial PortsEnable and Three-State .......................... 36 Added Timer Clock Timing ...................................... 41 Revised Timer Cycle Timing ..................................... 41 Updated Ordering Guide ......................................... 63 Rev. I Page 2 of 64 August 2013