ADSP-BF522KBCZ-3

Blackfin Embedded Processor ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor USB 2.0 high speed on-the-go (OTG) with integrated PHY Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, IEEE 802.3-compliant 10/100 Ethernet MAC 40-bit shifter Parallel peripheral interface (PPI), supporting ITU-R 656 RISC-like register and instruction model for ease of video data formats programming and compiler-friendly support Host DMA port (HOSTDP) Advanced debug, trace, and performance monitoring 2 dual-channel, full-duplex synchronous serial ports 2 Accepts a wide range of supply voltages for internal and I/O (SPORTs), supporting eight stereo I S channels operations. See Specifications on Page 28 12 peripheral DMAs, 2 mastered by the Ethernet MAC Programmable on-chip voltage regulator (ADSP-BF523/ 2 memory-to-memory DMAs with external request lines ADSP-BF525/ADSP-BF527 processors only) Event handler with 54 interrupt inputs Qualified for Automotive Applications. See Automotive Serial peripheral interface (SPI) compatible port Products on Page 87 2 UARTs with IrDA support 289-ball and 208-ball CSP BGA packages 2-wire interface (TWI) controller Eight 32-bit timers/counters with PWM support MEMORY 32-bit up/down counter with rotary support 132K bytes of on-chip memory (See Table 1 on Page 3 for L1 Real-time clock (RTC) and watchdog timer and L3 memory size details) 32-bit core timer External memory controller with glueless support for SDRAM 48 general-purpose I/Os (GPIOs), with programmable and asynchronous 8-bit and 16-bit memories hysteresis Flexible booting options from external flash, SPI, and TWI NAND flash controller (NFC) memory or from host devices including SPI, TWI, and UART Debug/JTAG interface Code security with Lockbox Secure Technology On-chip PLL capable of frequency multiplication one-time-programmable (OTP) memory Memory management unit providing memory protection WATCHDOG TIMER OTP MEMORY RTC VOLTAGE REGULATOR* JTAG TEST AND EMULATION COUNTER PERIPHERAL ACCESS BUS SPORT0 SPORT1 INTERRUPT GPIO UART1 CONTROLLER B PORT F UART0 NFC L1 INSTRUCTION L1 DATA DMA GPIO MEMORY MEMORY CONTROLLER PPI PORT G DMA ACCESS EAB 16 SPI BUS DCB USB TIMER7-1 GPIO DEB PORT H TIMER0 EXTERNAL PORT BOOT EMAC ROM FLASH, SDRAM CONTROL HOST DMA PORT J TWI *REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS Figure 1. Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TABLE OF CONTENTS Features ................................................................. 1 Clock Signals ...................................................... 16 Memory ................................................................ 1 Booting Modes ................................................... 18 Peripherals ............................................................. 1 Instruction Set Description .................................... 20 General Description ................................................. 3 Development Tools .............................................. 20 Portable Low Power Architecture ............................. 3 Additional Information ........................................ 21 System Integration ................................................ 3 Related Signal Chains ........................................... 22 Processor Peripherals ............................................. 3 Lockbox Secure Technology Disclaimer .................... 22 Blackfin Processor Core .......................................... 4 Signal Descriptions ................................................. 23 Memory Architecture ............................................ 5 Specifications ........................................................ 28 DMA Controllers .................................................. 9 Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Host DMA Port .................................................... 9 Processors ...................................................... 28 Real-Time Clock ................................................... 9 Operating Conditions for ADSP-BF523/ADSP-BF525/ Watchdog Timer ................................................ 10 ADSP-BF527 Processors .................................... 30 Timers ............................................................. 10 Electrical Characteristics ....................................... 32 Up/Down Counter and Thumbwheel Interface .......... 10 Absolute Maximum Ratings ................................... 37 Serial Ports ........................................................ 10 Package Information ............................................ 38 Serial Peripheral Interface (SPI) Port ....................... 11 ESD Sensitivity ................................................... 38 UART Ports ...................................................... 11 Timing Specifications ........................................... 39 TWI Controller Interface ...................................... 12 Output Drive Currents ......................................... 73 10/100 Ethernet MAC .......................................... 12 Test Conditions .................................................. 75 Ports ................................................................ 12 Environmental Conditions .................................... 79 Parallel Peripheral Interface (PPI) ........................... 13 289-Ball CSP BGA Ball Assignment ........................... 80 USB On-The-Go Dual-Role Device Controller ........... 14 208-Ball CSP BGA Ball Assignment ........................... 83 Code Security with Lockbox Secure Technology ......... 14 Outline Dimensions ................................................ 86 Dynamic Power Management ................................ 14 Surface-Mount Design .......................................... 87 ADSP-BF523/ADSP-BF525/ADSP-BF527 Automotive Products .............................................. 87 Voltage Regulation ........................................... 16 Ordering Guide ..................................................... 88 ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation ........................................... 16 REVISION HISTORY 7/13Rev. C to Rev. D Updated Development Tools .................................... 20 Corrected footnote 9 and added footnote 11 in Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors .......................................... 30 Rev. D Page 2 of 88 July 2013