2 dB LSB, 4-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Data Sheet ADRF5731 FEATURES FUNCTIONAL BLOCK DIAGRAM ADRF5731 Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 2 dB steps to 30 dB Low insertion loss 1.7 dB to 18 GHz 2.2 dB to 26 GHz 16 15 14 13 3.5 dB to 40 GHz 1 12 D4/SERIN VDD Attenuation accuracy SERIAL/ PARALLEL 11 D5/CLK 2 VSS INTERFACE (0.1 + 2.0%) of attenuation state up to 18 GHz 3 10 GND GND (0.2 + 2.5%) of attenuation state up to 26 GHz 4-BIT DIGITAL ATTENUATOR 4 9 ATTOUT (0.5 + 10.0%) of attenuation state up to 40 GHz ATTIN Typical step error 5 6 7 8 0.15 dB to 18 GHz PACKAGE BASE 0.20 dB to 26 GHz 0.60 dB to 40 GHz Figure 1. High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 26 dBm IP3: 50 dBm typical High RF input power handling: 26 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 230 ns 2.5 mm 2.5 mm, 16-terminal LGA package Pin compatible with ADRF5721, low frequency cutoff version APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5731 is a silicon, 4-bit digital attenuator with a 30 dB The ADRF5731 is pin compatible with the ADRF5721 low attenuation control range in 2 dB steps. frequency cutoff version, which operates from 9 kHz to 40 GHz. This device operates from 100 MHz to 40 GHz with better than The ADRF5731 RF ports are designed to match a characteristic 3.5 dB of insertion loss. The ATTIN port of the ADRF5720 has impedance of 50 . a radio frequency (RF) input power handling capability of 26 dBm The ADRF5731 comes in a 16-terminal, 2.5 mm 2.5 mm, average and 30 dBm peak for all states. RoHS compliant, land grid array (LGA) package and operates The ADRF5731 requires a dual supply voltage of +3.3 V and from 40C to +105C. 3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL) compatible controls. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182021 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. GND D3/SEROUT GND D2 GND PS GND LE 17000-001ADRF5731 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................8 Applications ....................................................................................... 1 Input Power Compression and Third-Order Intercept ......... 10 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Power Supply ............................................................................... 11 Revision History ............................................................................... 2 RF Input and Output ................................................................. 11 Specifications ..................................................................................... 3 Serial or Parallel Mode Selection ............................................. 12 Electrical Specifications ............................................................... 3 Serial Mode Interface ................................................................. 12 Timing Specifications .................................................................. 5 Parallel Mode Interface .............................................................. 13 Absolute Maximum Ratings ....................................................... 6 Applications Information .............................................................. 14 Thermal Resistance ...................................................................... 6 Evaluation Board ........................................................................ 14 Power Derating Curves ................................................................ 6 Probe Matrix Board ................................................................... 16 ESD Caution .................................................................................. 6 Packaging and Ordering Information ......................................... 17 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ................................................................... 17 Interface Schematics..................................................................... 7 Ordering Guide .......................................................................... 17 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 4/2021Rev. A to Rev. B 3/2020Rev. 0 to Rev. A Changes to RF Power Parameter, Table 1 ....................................... 4 Changes to tCH and tCO Parameters, Table 2 ................................... 5 Added Figure 8 and Figure 9 Renumbered Sequentially ........... 7 Changes to Table 3 ............................................................................. 6 Change to Figure 19 ......................................................................... 9 Changes to Power Supply Section ................................................ 11 Changes to Serial Mode Interface Section and Using SEROUT Added Power-Up State Section..................................................... 11 Section .............................................................................................. 12 Moved Serial or Parallel Mode Selection Section and Table 7 Deleted Figure 23 Renumbered Sequentially ............................ 12 Renumbered Sequentially ......................................................................12 Changes to Figure 25 ...................................................................... 12 9/2018Revision 0: Initial Version Rev. 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