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Blackfin Dual Core Embedded Processor ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 FEATURES MEMORY Dual-core symmetric high-performance Blackfin processor, Each core contains 148K bytes of L1 SRAM memory (proces- up to 500 MHz per core sor core-accessible) with multi-parity bit protection Each core contains two 16-bit MACs, two 40-bit ALUs, and a Up to 256K bytes of L2 SRAM memory with ECC protection 40-bit barrel shifter Dynamic memory controller provides 16-bit interface to a RISC-like register and instruction model for ease of single bank of DDR2 or LPDDR DRAM devices programming and compiler-friendly support Static memory controller with asynchronous memory inter- Advanced debug, trace, and performance monitoring face that supports 8-bit and 16-bit memories Pipelined Vision Processor provides hardware to process sig- 4 Memory-to-memory DMA streams, 2 of which feature CRC nal and image algorithms used for pre- and co-processing protection of video frames in ADAS or other video processing Flexible booting options from flash, SD EMMC, and SPI mem- applications ories and from SPI, link port and UART hosts Accepts a range of supply voltages for I/O operation. See Memory management unit provides memory protection Operating Conditions on Page 52 Off-chip voltage regulator interface 349-ball BGA package (19 mm 19 mm), RoHS compliant SYSTEM CONTROL BLOCKS PERIPHERALS EMULATOR PLL & POWER FAULT EVENT DUAL TEST & CONTROL MANAGEMENT MANAGEMENT CONTROL WATCHDOG 2 TWI 8 TIMER 1 COUNTER L2 MEMORY 2 PWM CORE 0 CORE 1 32K BYTE ROM 3 SPORT B B 256K BYTE 148K BYTE 148K BYTE 1 ACM PARITY BIT PROTECTED PARITY BIT PROTECTED ECC- L1 SRAM L1 SRAM PROTECTED INSTRUCTION/DATA INSTRUCTION/DATA SRAM 2 UART 112 GP I/O EMMC/RSI DMA SYSTEM 1 CAN 2 EMAC EXTERNAL WITH 2 IEEE 1588 BUS INTERFACES 2 SPI PIPELINED 4 LINK PORT CRC VISION PROCESSOR DYNAMIC STATIC MEMORY MEMORY CONTROLLER CONTROLLER VIDEO SUBSYSTEM 3 PPI HARDWARE PIXEL FUNCTIONS COMPOSITOR LPDDR 16 16 FLASH USB 2.0 HS OTG DDR2 SRAM Figure 1. Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2014 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 TABLE OF CONTENTS Features . 1 Operating Conditions . 52 Memory 1 Electrical Characteristics . 55 General Description . 3 Processor Absolute Maximum Ratings 59 Blackfin Processor Core 3 ESD Sensitivity . 59 Instruction Set Description . 4 Processor Package Information . 59 Processor Infrastructure . 5 Timing Specifications . 60 Memory Architecture 6 Output Drive Currents . 102 Video Subsystem 9 Test Conditions 103 Processor Safety Features 10 Environmental Conditions 105 Additional Processor Peripherals 11 ADSP-BF60x 349-Ball CSP BGA Ball Assignments 106 Power and Clock Management . 14 349-Ball CSP BGA Ball Assignment (Numerical by Ball Number) 106 System Debug 17 349-Ball CSP BGA Ball Assignment (Alphabetical by Pin Development Tools . 17 Name) . 108 Additional Information 18 349-Ball CSP BGA Ball Configuration . 110 Related Signal Chains 18 Outline Dimensions 111 ADSP-BF60x Detailed Signal Descriptions . 19 Surface-Mount Design 111 349-Ball CSP BGA Signal Descriptions . 23 Automotive Products 112 GP I/O Multiplexing for 349-Ball CSP BGA . 33 Ordering Guide . 112 ADSP-BF60x Designer Quick Reference 37 Specifications 52 REVISION HISTORY 2/14Rev. 0 to Rev. A Corrected the signal names in the following figures: DDR2 SDRAM Clock and Control Cycle Timing . 69 Added the system clock output specification and additional DDR2 SDRAM Controller Input AC Timing 70 peripheral external clocks in Clock Related Operating Condi- Mobile DDR SDRAM Clock and Control Cycle Timing . 72 tions on Page 53. These changes affect the following peripheral timing sections. Added Figure 29 and updated Table 42 in Enhanced Parallel Peripheral Interface Timing 74 Enhanced Parallel Peripheral Interface Timing 74 Corrected the t , t , t , t , and t HSPIDM SDSCIM SPICLK HDSM SPITDM Link Ports 78 specifications in Serial Peripheral Interface (SPI) PortMaster Serial PortsExternal Clock . 80 Timing 86 Serial Peripheral Interface (SPI) PortMaster Timing 86 Corrected the t specification in Serial Peripheral Interface HDSPID (SPI) PortSlave Timing . 88 Serial Peripheral Interface (SPI) PortSlave Timing 88 Corrected t in Serial Peripheral Interface (SPI) Port ADC Controller Module (ACM) Timing . 96 SRDYSCKM1 SPI RDY Timing . 92 Additional revisions include the following. Revised all parameters in Timer Cycle Timing . 94 Corrected S0SEL and S1SEL in Figure 8 Clock Relationships Corrected the timing diagram in ADC Controller Module and Divider Values . 54 (ACM) Timing 96 Revised the dynamic and static current tables CCLK Dynamic Removed TWI signals in footnote 3 in JTAG Test And Emula- Current per core (mA, with ASF = 1) 57 tion Port Timing 101 Static CurrentIDD DEEPSLEEP (mA) . 58 Added models to Automotive Products . 112 Corrected the t parameter in Asynchronous Page Mode WARE Read . 64 Corrected the timing diagram in Bus Request/Bus Grant . 69 Rev. A Page 2 of 112 February 2014