2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC Data Sheet AD9915 FEATURES FUNCTIONAL BLOCK DIAGRAM 2.5 GSPS internal clock speed AD9915 HIGH SPEED PARALLEL Integrated 12-bit DAC MODULATION PORT Frequency tuning resolution to 135 pHz 16-bit phase tuning resolution 12-bit amplitude scaling Programmable modulus Automatic linear and nonlinear frequency sweeping LINEAR SWEEP 2.5GSPS DDS CORE 12-BIT DAC capability BLOCK 32-bit parallel datapath interface 8 frequency/phase offset profiles Phase noise: 128 dBc/Hz (1 kHz offset at 978 MHz) Wideband SFDR < 57 dBc Serial or parallel input/output control REF CLK 1.8 V/3.3 V power supplies TIMING AND CONTROL MULTIPLIER Software and hardware controlled power-down 88-lead LFCSP package PLL REF CLK multiplier Phase modulation capability SERIAL OR PARALLEL DATA PORT Amplitude modulation capability Multichip synchronization Figure 1. APPLICATIONS Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulator Fast frequency hopping Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 10837-001AD9915 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 12-Bit DAC Output .................................................................... 20 Applications ....................................................................................... 1 DAC Calibration Output ........................................................... 20 Functional Block Diagram .............................................................. 1 Reconstruction Filter ................................................................. 20 Revision History ............................................................................... 2 REF CLK Clock Input (REF CLK/ ) ........................................ 21 General Description ......................................................................... 3 PLL Lock Indication .................................................................. 22 Specifications ..................................................................................... 4 Output Shift Keying (OSK) ....................................................... 22 DC Specifications ......................................................................... 4 Digital Ramp Generator (DRG) ............................................... 23 AC Specifications .......................................................................... 5 Power-Down Control ................................................................ 27 Absolute Maximum Ratings ............................................................ 8 Programming and Function Pins ................................................. 28 Thermal Performance .................................................................. 8 Serial Programming ....................................................................... 31 ESD Caution .................................................................................. 8 Control InterfaceSerial Input/Output ................................. 31 Pin Configuration and Function Descriptions ............................. 9 General Serial Input/Output Operation .................................. 31 Typical Performance Characteristics ........................................... 12 Instruction Byte .......................................................................... 31 Equivalent Circuits ......................................................................... 16 Serial Input/Output Port Pin Descriptions ............................. 31 Theory of Operation ...................................................................... 17 Serial Input/Output Timing Diagrams .................................... 32 Single Tone Mode ....................................................................... 17 MSB/LSB Transfers .................................................................... 32 Profile Modulation Mode .......................................................... 17 Parallel Programming (8-/16-Bit) ................................................ 33 Digital Ramp Modulation Mode .............................................. 17 Multiple Chip Synchronization .................................................... 34 Parallel Data Port Modulation Mode ....................................... 17 Register Map and Bit Descriptions .............................................. 36 Programmable Modulus Mode ................................................. 17 Register Bit Descriptions ........................................................... 41 Mode Priority .............................................................................. 18 Outline Dimensions ....................................................................... 47 Functional Block Detail ................................................................. 19 Ordering Guide .......................................................................... 47 DDS Core ..................................................................................... 19 REVISION HISTORY 6/2016Rev. E to Rev. F 7/2013Rev. A to Rev. B Changes to Figure 17 and Figure 19 ............................................. 14 Change to CMOS Logic Outputs Parameter, Table 1 ................... 4 Changes to Table 2 ............................................................................. 7 1/2016Rev. D to Rev. E Changes to DDS Core Section ...................................................... 19 Changes to DDS Core Section ...................................................... 19 Changes to Phase-Locked Loop (PLL) Multiplier Section ....... 21 Change to Figure 30 ....................................................................... 19 Changed PLL Charge Pump Section to PLL Charge Pump/ Updated Outline Dimensions ....................................................... 47 Total Feedback Divider Section Changes to Table 8, PLL Loop Filter Components Section, and Figure 34 ....................... 22 1/2014Rev. C to Rev. D Change to Table 16 ......................................................................... 36 Change to Maximum DAC Calibration Time Parameter ........... 5 Changes to Bits 15:8 , Table 19 ................................................... 43 Change to Figure 23 ....................................................................... 15 Changes to DAC Calibration Output Section ............................. 20 8/2012Rev. 0 to Rev. A Change to Address 0x02, Table 16 ................................................ 36 Changed External Clock Frequency from 3.5 GHz to 2.5 GHz Changes to Table 19 ........................................................................ 43 and Differential Input Voltage Unit from mV p-p to V p-p ........ 4 Updated Outline Dimensions ....................................................... 47 11/2013Rev. B to Rev. C Changes to Table 2 ............................................................................ 5 7/2012Revision 0: Initial Version Changes to Programming and Function Pins Section .............. 30 Rev. F Page 2 of 47