+5 Volt, Serial Input, a Dual 12-Bit DAC AD8522 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete Dual 12-Bit DAC V DD No External Components +5 V Single-Supply Operation 610% CS OP CLK DAC A AMP V 4.095 V Full Scale (1 mV/LSB) LATCH OUTA CLK DAC A 12 A REGISTER Buffered Voltage Outputs D Low Power: 5 mW/DAC SDI BANDGAP REF Space Saving 1.5 mm Height SO-14 Package (DATA) 12 REFERENCE BUF SHIFT REGISTER V REF APPLICATIONS Digitally Controlled Calibration REF BUF Servo Controls D DAC B SDO Process Control Equipment REGISTER 12 OP Computer Peripherals DAC B V AMP OUTB LDA CONTROL B Portable Instrumentation LOGIC LDB Cellular Base Stations Voltage Adjustment AD8522 DGND MSB AGND RS GENERAL DESCRIPTION inputs. A serial data output allows the user to easily daisy-chain The AD8522 is a complete dual 12-bit, single-supply, voltage multiple devices in conjunction with a chip select input. A reset output DAC in a 14-pin DIP, or SO-14 surface mount package. RS input sets the outputs to zero scale or midscale, as deter- Fabricated in a CBCMOS process, features include a serial digi- mined by the input MSB. tal interface, onboard reference, and buffered voltage output. The output 4.095 V full scale is laser trimmed to maintain accu- Ideal for +5 V-only systems, this monolithic device offers low racy over the operating temperature range of the device, and cost and ease of use, and requires no external components to gives the user an easy-to-use one-millivolt-per-bit resolution. A realize the full performance of the device. 2.5 V reference output is also available externally for other data The serial digital interface allows interfacing directly to numer- acquisition circuitry, and for ratiometric applications. The out- ous microcontroller ports, with a simple high speed, three-wire put buffers are capable of driving 5 mA. data, clock, and load strobe format. The 16-bit serial word con- The AD8522 is available in the 14-pin plastic DIP and low pro- tains the 12-bit data word and DAC select address, which is de- file 1.5 mm SOIC-14 packages. coded internally or can be decoded externally using LDA, LDB 0.6 PACKAGE TYPES AVAILABLE V = +4.5V DD 0.4 T = 55C, +25C, +85C, +125C A +25C 0.2 55C 0 0.2 0.4 PDIP-14 0.6 +85C SO-14 +125C 0.8 1.0 0 1024 2048 3072 4096 DIGITAL INPUT CODE Decimal Figure 1. Linearity Error vs. Digital Code & Temperature REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 LINEARITY ERROR LSBAD8522SPECIFICATIONS ( V = +5.0 V 6 10%, R = No Load, 408C T +858C, both DACs tested, unless DD L A otherwise noted) ELECTRICAL CHARACTERISTICS Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE 1 Resolution N 12 Bits Relative Accuracy INL -1.5 0.5 +1.5 LSB Differential Nonlinearity DNL Monotonic -1 0.5 +1 LSB Zero-Scale Error V Data = 000 +0.5 +3 mV ZSE H 2 Full-Scale Voltage V Data = FFF 4.079 4.095 4.111 Volts FS H 2, 3 Full-Scale Tempco TCV 15 ppm/C FS MATCHING PERFORMANCE Linearity Matching Error V A/B 1 LSB FS ANALOG OUTPUT Output Current I Data = 800 , V 3 LSB 5mA OUT H OUT Load Regulation at Half-Scale LD R = 402 to , Data = 800 1 3 LSB REG L H 3 Capacitive Load C No Oscillation 500 pF L REFERENCE OUTPUT Output Voltage V 2.484 2.500 2.516 V REF 4 Output Source Current I V < 18 mV 5 mA REF REF Line Rejection LN 0.025 0.08 %/V REJ Load Regulation LD I = 0 to 5 mA, Data = 800 0.025 0.1 %/mA REG REF H LOGIC INPUTS & OUTPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10 A IL 3 Input Capacitance C 10 pF IL Logic Output Voltage Low V I = 1.6 mA 0.4 V OL OL Logic Output Voltage High V I = 400 A 3.5 V OH OH 3, 5 TIMING SPECIFICATIONS Clock Width High t 35 ns CH Clock Width Low t 35 ns CL Load Pulse Width t 25 ns LDW Data Setup t 10 ns DS Data Hold t 20 ns DH Clear Pulse Width t 20 ns CLRW Load Setup t 10 ns LD1 Load Hold t 10 ns LD2 Select t 30 ns CSS Deselect t 30 ns CSH Clock to SDO Propagation Delay t 20 45 80 ns PD 3, 5 AC CHARACTERISTICS 6 Voltage Output Settling Time t To 1 LSB of Final Value 16 s S Crosstalk C Signal Measured at DAC Output, T While Changing Opposite LDA/B 38 dB DAC Glitch Q Half-Scale Transition 13 nV s Digital Feedthrough D Signal Measured at DAC Output, FT While Changing Data Without LDA/B 2 nV s SUPPLY CHARACTERISTICS Positive Supply Current I V = 5.5 V, V = 2.4 V or V = 0.8 V 3 5 mA DD DD IH IL V = 5 V, V = 0 V 1 2 mA DD IL 7 Power Dissipation P V = 5 V, V = 2.4 V or V = 0.8 V 15 25 mW DISS DD IH IL V = 5 V, V = 0 V 5 10 mW DD IL Power Supply Sensitivity PSS V = 5% 0.002 0.004 %/% DD NOTES 1 1 LSB = 1 mV for 0 V to +4.095 V output range. 2 Includes internal voltage reference error. 3 These parameters are guaranteed by design and not subject to production testing. 4 Very little sink current is available at the V pin. Use external buffer if setting up a virtual ground. REF 5 All input control signals are specified with t = t = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. r f 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. 7 Power Dissipation is calculated I 5 V. DD Specifications subject to change without notice. 2 REV. A