AD7233ANZ

2 LC MOS a 12-Bit Serial Mini-DIP DACPORT AD7233 FUNCTIONAL BLOCK DIAGRAM FEATURES 12-Bit CMOS DAC with V DD On-Chip Voltage Reference Output Amplifier 2R 2R 5 V to +5 V Output Range Serial Interface 300 kHz DAC Update Rate V OUT 12-BIT Small Size: 8-Pin Mini-DIP DAC Nonlinearity: 1/2 LSB T to T MIN MAX 12 Low Power Dissipation: 100 mW Typ GND DAC APPLICATIONS LATCH Process Control Industrial Automation 12 AD7233 Digital Signal Processing Systems V SS INPUT SHIFT Input/Output Ports REGISTER SDIN SCLK SYNC LDAC GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7233 is a complete 12-bit, voltage-output, digital-to- 1. Complete 12-Bit DACPORT . analog converter with output amplifier and Zener voltage reference 2. The AD7233 is a complete, voltage output, 12-bit DAC on a all in an 8-lead package. No external trims are required to single chip. This single-chip design is inherently more reli- achieve full specified performance. The data format is twos able than multichip designs. complement, and the output range is 5 V to +5 V. 3. Simple 3-wire interface to most microcontrollers and DSP The AD7233 features a fast, versatile serial interface which processors. allows easy connection to both microcomputers and 16-bit digital 4. DAC Update Rate300 kHz. signal processors with serial ports. When the SYNC input is taken low, data on the SDIN pin is clocked into the input shift 5. Space Saving 8-Lead Package. register on each falling edge of SCLK. On completion of the 16-bit data transfer, bringing LDAC low updates the DAC latch with the lower 12 bits of data and updates the output. Alterna- tively, LDAC can be tied permanently low, and in this case the DAC register is automatically updated with the contents of the shift register when all sixteen data bits have been clocked in. The serial data may be applied at rates up to 5 MHz allowing a DAC update rate of 300 kHz. For applications which require greater flexibility and unipolar output ranges with single supply operation, please refer to the AD7243 data sheet. The AD7233 is fabricated on Linear Compatible CMOS 2 (LC MOS), an advanced, mixed-technology process. It is pack- aged in an 8-lead DIP package. DACPORT is a registered trademark of Analog Devices, Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 Analog Devices, Inc., 20012 2 (V = +12 V to +15 V, V = 12 V to 15 V, GND = 0 V, R = 2 k , C = 100 pF 1 DD SS L L AD7233SPECIFICATIONS to GND. All specifications T to T unless otherwise noted.) MIN MAX Parameter A Version B Version Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 12 12 Bits 3 Relative Accuracy 1 1/2 LSB max 3 Differential Nonlinearity 0.9 0.9 LSB max Guaranteed Monotonic 3 Bipolar Zero Error 6 6 LSB max DAC Latch Contents 0000 0000 0000 3 Full-Scale Error 8 8 LSB max 4 Full-Scale Temperature Coefficient 30 30 ppm of FSR/C typ Guaranteed By Process DIGITAL INPUTS Input High Voltage, V 2.4 2.4 V min INH Input Low Voltage, V 0.8 0.8 V max INL Input Current I 1 1 A max V = 0 V to V IN IN DD 4 Input Capacitance 8 8 pF max ANALOG OUTPUTS Output Voltage Range 5 5V 4 DC Output Impedance 0.5 0.5 typ 4 AC CHARACTERISTICS Voltage Output Settling Time Settling Time to Within 1/2 LSB of Final Value Positive Full-Scale Change 10 10 s max Typically 4 s DAC Latch 100 .000 to 011 .111 Negative Full-Scale Change 10 10 s max Typically 5 s DAC Latch 011 .111 to 100 .000 3 Digital-to-Analog Glitch Impulse 30 30 nV secs typ DAC Latch Contents Toggled Between All 0s and all 1s 3 Digital Feedthrough 10 10 nV secs typ LDAC = High POWER REQUIREMENTS V Range 10.8/16.5 10.8/16.5 V min/V max For Specified Performance Unless Otherwise Stated DD V Range 10.8/16.5 10.8/16.5 V min/V max For Specified Performance Unless Otherwise Stated SS I 10 10 mA max Output Unloaded Typically 7 mA at Thresholds DD I 2 2 mA max Output Unloaded Typically 1 mA at Thresholds SS NOTES 1 Temperature Ranges are as follows: A, B Versions: 40C to +85C. 2 Power Supply Tolerance: A, B Versions: 10%. 3 See Terminology. 4 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. (V = +10.8 V to +16.5 V, V = 10.8 V to 16.5 V, GND = O V, R = 2 k , C = 100 pF. All DD SS L L 1, 2 TIMING CHARACTERISTICS Specifications T to T unless otherwise noted.) MIN MAX Limit at 25 C, T , T MIN MAX Parameter (All Versions) Unit Conditions/Comments 3 t 200 ns min SCLK Cycle Time 1 t 15 ns min SYNC to SCLK Falling Edge Setup Time 2 t 70 ns min SYNC to SCLK Hold Time 3 t 0 ns min Data Setup Time 4 t 40 ns min Data Hold Time 5 t 0 ns min SYNC High to LDAC Low 6 t 20 ns min LDAC Pulsewidth 7 t 0 ns min LDAC High to SYNC Low 8 NOTES 1 Sample tested at 25C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 3. 3 SCLK Mark/Space Ratio range is 40/60 to 60/40. 2 REV. B