AD6650ABC

AD6650 Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver AD6650 FEATURES Smart antenna systems 116 dB dynamic range Software radios Digital VGA In-building wireless telephony I/Q demodulators PRODUCT DESCRIPTION Active low-pass filters The AD6650 is a diversity intermediate frequency-to-baseband Dual wideband ADC (IF-to-baseband) receiver for GSM/EDGE. This narrow-band Programmable decimation and channel filters receiver consists of an integrated DVGA, IF-to-baseband I/Q VCO and phase-locked loop circuitry demodulators, low-pass filtering, and a dual wideband ADC. Serial data output ports The chip can accommodate IF input from 70 MHz to 260 MHz. Intermediate frequencies of 70 MHz to 260 MHz The receiver architecture is designed such that only one external 10 dB noise figure surface acoustic wave (SAW) filter for main and one for diversity +43 dBm input IP2 at 70 MHz IF are required in the entire receive signal path to meet GSM/EDGE 9.5 dBm input IP3 at 70 MHz IF blocking requirements. 3.3 V I/O and CMOS core Microprocessor interface Digital decimation and filtering circuitry provided on-chip JTAG boundary scan remove unwanted signals and noise outside the channel of interest. Programmable RAM coefficient filters allow antialiasing, APPLICATIONS matched filtering, and static equalization functions to be combined PHS or GSM/EDGE single carrier, diversity receivers in a single cost-effective filter. The output of the channel filters Microcell and picocell systems is provided to the user via serial output I/Q data streams. Wireless local loop FUNCTIONAL BLOCK DIAGRAM TWEAK GAIN AD6650 GSM/ EDGE IF RECEIVER DAC AGC LP RELIN FILTER CTRL I LPF TH TH 4 7 PROG. AIN FINE 12-BIT COARSE MUX ORDER ORDER FIR BIST VGA DCC ADC DCC CIC IIR (RCF) AIN LPF Q SCLK CPOUT SDFS 0 PLL/ SERIAL LF /4 REF SDO0 90 VCO PORT VLDO SDO1 DR Q LPF TH TH BIN 4 7 PROG. FINE 12-BIT COARSE VGA MUX ORDER ORDER FIR BIST DCC ADC DCC CIC IIR (RCF) BIN LPF I AGC LP RELIN FILTER CTRL DAC TWEAK GAIN CLK JTAG MICRO DIVIDER Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20062007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. TRST TCLK TDI TDO TMS SYNC CLK CLK AVDD AGND DVDD DGND RESET CS R/W DS MODE 2:0 A 2:0 D 7:0 DTACK 03683-001AD6650 TABLE OF CONTENTS Features .............................................................................................. 1 LO Synthesis................................................................................ 22 Applications....................................................................................... 1 LDO.............................................................................................. 23 Product Description......................................................................... 1 AGC Loop/Relinearization ....................................................... 23 Functional Block Diagram .............................................................. 1 Serial Output Data Port............................................................. 24 Revision History ............................................................................... 2 Application Information................................................................ 26 Specifications..................................................................................... 3 Required Settings and Start-up Sequence for DC Correction ....................................................................................................... 26 Explanation of Test Levels........................................................... 3 Clocking the AD6650 ................................................................ 26 AC Specifications.......................................................................... 3 Driving the Analog Inputs ........................................................ 27 Digital Specifications ................................................................... 4 External Reference ..................................................................... 27 Electrical Characteristics............................................................. 5 Power Supplies............................................................................ 27 General Timing Characteristics ................................................. 5 Digital Outputs ........................................................................... 28 Microprocessor Port Timing Characteristics ........................... 6 Grounding ................................................................................... 28 Timing Diagrams.......................................................................... 7 Layout Information.................................................................... 28 Absolute Maximum Ratings.......................................................... 10 Chip Synchronization ................................................................ 29 Thermal Characteristics ............................................................ 10 Microport Control.......................................................................... 30 ESD Caution................................................................................ 10 External Memory Map .............................................................. 30 Pin Configuration and Function Descriptions........................... 11 Access Control Register (ACR) ................................................ 30 Typical Performance Characteristics ........................................... 13 Channel Address Register (CAR) ............................................ 30 Terminology .................................................................................... 14 Special Function Registers ........................................................ 30 Equivalent Circuits ......................................................................... 15 Data Address Registers .............................................................. 31 Theory of Operation ...................................................................... 16 Write Sequencing ....................................................................... 31 Analog Front End....................................................................... 16 Read Sequencing ........................................................................ 31 Digital Back End......................................................................... 16 Read/Write Chaining................................................................. 31 DC Correction ............................................................................ 16 Programming Modes................................................................. 31 Fourth-Order Cascaded Integrator Comb Filter (CIC4) ...... 17 JTAG Boundary Scan................................................................. 32 Infinite Impulse Response (IIR) Filter..................................... 18 Register Map ................................................................................... 33 RAM Coefficient Filter .............................................................. 18 Register Details........................................................................... 39 Composite Filter ......................................................................... 19 Outline Dimensions....................................................................... 44 Fine DC Correction ................................................................... 20 Ordering Guide .......................................................................... 44 Peak Detector DC Correction Ranging................................... 20 User-Configurable Built-In Self-Test (BIST) .......................... 21 REVISION HISTORY 1/07Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Specifications................................................................ 3 Changes to Figure 18...................................................................... 13 Changes to Power Supplies Section.............................................. 27 Changes to Ordering Guide .......................................................... 44 3/06Revision 0: Initial Version Rev. A Page 2 of 44