A1 W1 B1 A2 W2 B2 A3 W3 B3 A4 W4 B4 2 Quad Channel, 128-/256-Position, I C/SPI, Nonvolatile Digital Potentiometer Data Sheet AD5124/AD5144/AD5144A FEATURES FUNCTIONAL BLOCK DIAGRAM V V LOGIC DD LRDAC 10 k and 100 k resistance options Resistor tolerance: 8% maximum AD5124/AD5144 Wiper current: 6 mA POWER-ON RDAC1 RESET Low temperature coefficient: 35 ppm/C INPUT REGISTER 1 Wide bandwidth: 3 MHz Fast start-up time < 75 s RESET RDAC2 Linear gain setting mode DIS INPUT REGISTER 2 Single- and dual-supply operation SCLK/SCL SERIAL RDAC3 Independent logic supply: 1.8 V to 5.5 V INTERFACE SDI/SDA 7/8 INPUT Wide operating temperature: 40C to +125C REGISTER 3 SYNC/ADDR0 4 mm 4 mm package option RDAC4 SDO/ADDR1 APPLICATIONS INPUT REGISTER 4 Portable electronics level adjustment EEPROM LCD panel brightness and contrast controls MEMORY Programmable filters, delays, and time constants Programmable power supplies GND V WP SS Figure 1. AD5124/AD5144 24-Lead LFCSP GENERAL DESCRIPTION The AD5124/AD5144/AD5144A potentiometers provide a The AD5124/AD5144/AD5144A are available in a compact, nonvolatile solution for 128-/256-position adjustment applications, 24-lead, 4 mm 4 mm LFCSP and a 20-lead TSSOP. The parts offering guaranteed low resistor tolerance errors of 8% and up to are guaranteed to operate over the extended industrial temperature 6 mA current density in the Ax, Bx, and Wx pins. range of 40C to +125C. The low resistor tolerance and low nominal temperature coefficient Table 1. Family Models simplify open-loop applications as well as applications requiring Model Channel Position Interface Package tolerance matching. 1 2 AD5123 Quad 128 I C LFCSP 2 The linear gain setting mode allows independent programming AD5124 Quad 128 SPI/I C LFCSP of the resistance between the digital potentiometer terminals, AD5124 Quad 128 SPI TSSOP 1 2 through the R and R string resistors, allowing very accurate AW WB AD5143 Quad 256 I C LFCSP 2 resistor matching. AD5144 Quad 256 SPI/I C LFCSP AD5144 Quad 256 SPI TSSOP The high bandwidth and low total harmonic distortion (THD) 2 AD5144A Quad 256 I C TSSOP ensure optimal performance for ac signals, making these devices AD5122 Dual 128 SPI LFCSP/TSSOP suitable for filter design. 2 AD5122A Dual 128 I C LFCSP/TSSOP The low wiper resistance of only 40 at the ends of the resistor AD5142 Dual 256 SPI LFCSP/TSSOP array allow for pin-to-pin connection. 2 AD5142A Dual 256 I C LFCSP/TSSOP 2 2 The wiper values can be set through an SPI-/I C-compatible digital AD5121 Single 128 SPI/I C LFCSP 2 interface that is also used to read back the wiper register and AD5141 Single 256 SPI/I C LFCSP EEPROM contents. 1 Two potentiometers and two rheostats. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 10877-001AD5124/AD5144/AD5144A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RDAC Register and EEPROM .................................................. 23 Applications ....................................................................................... 1 Input Shift Register .................................................................... 23 Functional Block Diagram .............................................................. 1 Serial Data Digital Interface Selection, DIS ............................ 23 General Description ......................................................................... 1 SPI Serial Data Interface ............................................................ 23 2 Revision History ............................................................................... 2 I C Serial Data Interface ............................................................ 25 2 Functional Block DiagramsTSSOP ............................................ 3 I C Address .................................................................................. 25 Specifications ..................................................................................... 4 Advanced Control Modes ......................................................... 27 Electrical CharacteristicsAD5124 .......................................... 4 EEPROM or RDAC Register Protection ................................. 28 Electrical CharacteristicsAD5144 and AD5144A ................ 7 Load RDAC Input Register (LRDAC) ..................................... 28 Interface Timing Specifications ................................................ 10 RDAC Architecture .................................................................... 31 Shift Register and Timing Diagrams ....................................... 11 Programming the Variable Resistor ......................................... 31 Absolute Maximum Ratings .......................................................... 13 Programming the Potentiometer Divider ............................... 32 Thermal Resistance .................................................................... 13 Terminal Voltage Operating Range ......................................... 32 ESD Caution ................................................................................ 13 Power-Up Sequence ................................................................... 32 Pin Configurations and Function Descriptions ......................... 14 Layout and Power Supply Biasing ............................................ 32 Typical Performance Characteristics ........................................... 17 Outline Dimensions ....................................................................... 33 Test Circuits ..................................................................................... 22 Ordering Guide .......................................................................... 34 Theory of Operation ...................................................................... 23 REVISION HISTORY 7/2019Rev. B to Rev. C Changes to Table 7 .......................................................................... 13 Added Endnote 2, Table 14 ........................................................... 26 Changes to Figure 11 and Table 11 .............................................. 16 Added Endnote 2, Table 20 ........................................................... 29 Changes to Figure 20 ...................................................................... 18 Updated Outline Dimensions ....................................................... 33 Added Figure 21 Renumbered Sequentially .............................. 18 Changes to Figure 24 ...................................................................... 19 7/2017Rev. A to Rev. B Change to Linear Gain Setting Mode Section ............................ 27 Changed LFCSP WQ to LFCSP .................................. Throughout Change to RDAC Architecture Section ....................................... 31 Changes to Features Section............................................................ 1 Updated Outline Dimensions ....................................................... 33 Changes to Logic Supply Current Parameter, Table 2 ................. 5 Added Note 12 to Data Retention Parameter, Table 2 12/2012Rev. 0 to Rev. A Renumbered Sequentially ................................................................ 6 Changes to Table 12 and Table 13 ................................................ 25 Changes to Logic Supply Current Parameter, Table 3 ................. 8 Added Note 12 to Data Retention Parameter, Table 3 10/2012Revision 0: Initial Version Renumbered Sequentially ................................................................ 9 Rev. C Page 2 of 36