Product Information

ES1010SI

ES1010SI electronic component of Intel

Datasheet
Hot Swap Controller 1-CH 13.8V N-Channel Positive Voltage 8-Pin SOIC T/R

Manufacturer: Intel
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Price (USD)

1: USD 7.6899 ea
Line Total: USD 7.69

0 - Global Stock
MOQ: 1  Multiples: 1000
Pack Size: 1000
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 1
Multiples : 1000

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ES1010SI
Intel

1 : USD 13.671
25 : USD 6.7987
100 : USD 5.5944

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 1
Multiples : 1000

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ES1010SI
Intel

1 : USD 7.6899
25 : USD 5.8741
100 : USD 5.035
500 : USD 4.468
1000 : USD 3.5834

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 1
Multiples : 1

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ES1010SI
Intel

1 : USD 9.0216

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May


Multiples : 1

Stock Image

ES1010SI
Intel


0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May


Multiples : 1

Stock Image

ES1010SI
Intel


     
Manufacturer
Product Category
Packaging
Package Height
Package Length
Package Width
Pcb Changed
Mounting
Lead Shape
Type
Fault Management
External Fet
Number Of Channels
Minimum Operating Supply Voltage V
Typical Operating Supply Voltage V
Maximum Operating Supply Voltage V
External Sense Resistor
Minimum Operating Temperature °C
Maximum Operating Temperature °C
Standard Package Name
Supplier Package
Pin Count
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Enpirion Power Datasheet ES1010SI 12V Hot-Swap Power Distribution Controllers DS-1044 Datasheet The Altera Enpirion ES1010SI is a fully featured hot-swap Features power controller that targets +12V applications. The Hot-swap Single Power Distribution Control for +12V ES1010SI has an integrated charge pump, which can generate Overcurrent Fault Isolation a higher (6.5V) gate drive to improve efficiency. Programmable Current Regulation Level This IC features programmable overcurrent (OC) detection, Programmable Current Regulation Time to Latch-Off current regulation (CR) with time delay to latch-off and soft- Rail-to-Rail Common Mode Input Voltage Range start. Enhanced Internal Charge Pump Drives N-Channel The current regulation level is set by 2 external resistors MOSFET gate to 6.5V above IC bias. R sets the CR Vth and the other is a low ohmic sense ISET- Undervoltage and Overcurrent Latch Indicators resistor across, which the CR Vth is developed. The CR Adjustable Turn-On Ramp duration is set by an external capacitor on the CLTIM pin, Protection During Turn-On which is charged with a 20A current once the CR Vth level is reached. The IC then quickly pulls down the GATE output Two Levels of Overcurrent Detection Provide Fast latching off the pass FET. Response to Varying Fault Conditions 1s Response Time to Dead Short Pb-Free (RoHS Compliant) Applications FPGA, DSP, and ASIC power protection Power Distribution Control Hot Plug Components and Circuitry Application Circuits - High Side Controller LOAD + - 1 8 EN ES1010SI 2 7 POK 3 6 OC 4 5 +12V +V SUPPLY TO BE CONTROLLED 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no 101 Innovation Drive Registered responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed San Jose, CA 95134 to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com March 2014 Altera Corporation Subscribe 09617 March 14, 2014 Rev APage 2 Ordering Information PART NUMBER PART TEMPERATURE PACKAGE PKG. (Notes 1, 3) MARKING RANGE (C) (Pb-free) DWG. ES1010SI 1010 -40 to +85 8 Ld SOIC M8.15 EVB-ES1010SI Evaluation Platform NOTES: 1. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.. Pin Configuration ES1010SI (8 LD SOIC) TOP VIEW ISET- 1 8 EN ISEN+ 2 7 POK GATE 3 6 CLTIM GND 4 5 VIN Pin Descriptions PIN NO. SYMBOL FUNCTION DESCRIPTION 1 ISET- Current Set Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. 2 ISEN+ Current Sense Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. 3 GATE External FET Gate Drive Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground Pin sets the turn-on ramp. At turn-on this capacitor will be charged to V +6.5V by an 14A IN current source. 4 GND Chip Return 5 VIN Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated GND +12V supply. 6 CLTIM Current Limit Timing Connect a capacitor from this pin to ground. This capacitor determines the time delay between Capacitor an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93k x CLTIM. 7 POK Power Good Indicator Indicates that the voltage on the ISEN+ pin is satisfactory. POK is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN+) is less than the UV level for the particular IC. 8 EN Power-ON EN is used to control and reset the chip. The chip is enabled when EN pin is driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a current limit time-out, the chip is reset by a low level signal applied to this pin. This input has 20A pull-up capability. ES1010SI 12V Hot-Swap Power Distribution Controllers March 2014 Altera Corporation 09617 March 14, 2014 Rev A

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
ALTERA
Altera (part of the Intel Group)
Altera (VA)
Altera Corporation
INTEL (ALTERA)
Intel (CPU)
Intel (formerly Altera)
Intel / Altera
INTEL / LEVEL ONE

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