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MT41K256M16LY-107:N

MT41K256M16LY-107:N electronic component of Alliance Memory

Datasheet
DRAM 4G 256Mx16 DDR3
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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Obsolete

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0 - WHS 1

MOQ : 1
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MT41K256M16LY-107:N
Alliance Memory

1 : USD 6.9795
10 : USD 4.7736
25 : USD 4.6872
50 : USD 4.6548
100 : USD 4.32
250 : USD 4.32
500 : USD 4.2012
1000 : USD 4.1364
2000 : USD 4.0068
N/A

Obsolete

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Additional Infomation About Product

4Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM MT41K1G4 128 Meg x 4 x 8 banks MT41K512M8 64 Meg x 8 x 8 banks MT41K256M16 32 Meg x 16 x 8 banks Self refresh temperature (SRT) Description Automatic self refresh (ASR) DDR3L SDRAM (1.35V) is a low voltage version of the Write leveling DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM Multipurpose register (Die Rev :E) data sheet specifications when running in Output driver calibration 1.5V compatible mode. Options Marking Features Configuration V = V = 1.35V (1.2831.45V) DD DDQ 1 Gig x 4 1G4 Backward compatible to V = V = 1.5V 0.075V DD DDQ 512 Meg x 8 512M8 Supports DDR3L devices to be backward com- 256 Meg x 16 256M16 patible in 1.5V applications FBGA package (Pb-free) x4, x8 Differential bidirectional data strobe 78-ball (9mm x 10.5mm) Rev. E RH 8n-bit prefetch architecture 78-ball (7.5mm x 10.6mm) Rev. N RG Differential clock inputs (CK, CK ) 78-ball (8mm x 10.5mm) Rev. P DA 8 internal banks FBGA package (Pb-free) x16 Nominal and dynamic on-die termination (ODT) 96-ball (9mm x 14mm) Rev. E HA for data, strobe, and mask signals 96-ball (7.5mm x 13.5mm) Rev. N LY Programmable CAS (READ) latency (CL) 96-ball (8mm x 14mm) Rev. P TW Programmable posted CAS additive latency (AL) Timing cycle time Programmable CAS (WRITE) latency (CWL) 938ps CL = 14 (DDR3-2133) -093 Fixed burst length (BL) of 8 and burst chop (BC) of 4 1.07ns CL = 13 (DDR3-1866) -107 (via the mode register set MRS ) 1.25ns CL = 11 (DDR3-1600) -125 Selectable BC4 or BL8 on-the-fly (OTF) Operating temperature Self refresh mode Commercial (0C T +95C) None C T of 105C C Industrial (40C T +95C) IT C 64ms, 8192-cycle refresh up to 85C Automotive (40C T +105C) AT C 32ms, 8192-cycle refresh at >85C to 95C Revision :E/:N/:P 16ms, 8192-cycle refresh at >95C to 105C Table 1: Key Timing Parameters t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) 1, 2 -093 2133 14-14-14 13.09 13.09 13.09 1 -107 1866 13-13-13 13.91 13.91 13.91 -125 1600 11-11-11 13.75 13.75 13.75 1. Backward compatible to 1600, CL = 11 (-125). Notes: 2. Backward compatible to 1866, CL = 13 (-107). 09005aef85af8fa8 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 4Gb DDR3L.pdf - Rev. R 09/18 EN 2017 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.4Gb: x4, x8, x16 DDR3L SDRAM Description Table 2: Addressing Parameter 1 Gig x 4 512 Meg x 8 256 Meg x 16 Configuration 128 Meg x 4 x 8 banks 64 Meg x 8 x 8 banks 32 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 64K (A 15:0 ) 64K (A 15:0 ) 32K (A 14:0 ) Bank address 8 (BA 2:0 ) 8 (BA 2:0 ) 8 (BA 2:0 ) Column address 2K (A 11, 9:0 ) 1K (A 9:0 ) 1K (A 9:0 ) Page size 1KB 1KB 2KB Figure 1: DDR3L Part Numbers ( 1 3 *LJ * H 7 0HJ ,QGXVWULDO WHPSHUDWXUH ,7 Y 5H 0DUN XWRPRWLYH WHPSHUDWXUH 7 EDOO PP PP )%* ( EDOO PP PP )%* 1 6SHHG *UDGH W EDOO PP PP )%* 3 &. QV &/ ( EDOO PP PP )%* W EDOO PP PP )%* 1 W &. QV &/ EDOO PP PP )%* 3 7: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on Note:

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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