AS7C34096A-12JIN

August 2004 AS7C34096A 3.3V 512K 8 CMOS SRAM Equal access and cycle times Features CE, OE inputs Easy memory expansion with Pin compatible to AS7C34096 TTL-compatible, three-state I/O Industrial and commercial temperature JEDEC standard packages Organization: 524,288 words 8 bits - 400 mil 36-pin SOJ Center power and ground pins - 44-pin TSOP 2 High speed ESD protection 2000 volts - 10/12/15/20 ns address access time Latch-up current 200 mA - 4/5/6/7 ns output enable access time Low power consumption: ACTIVE Pin arrangements - 650 mW / max 10 ns Low power consumption: STANDBY 36-pin SOJ (400 mil) - 28.8 mW / max CMOS A0 1 36 NC A1 2 35 A18 A2 3 34 A17 A3 4 33 A16 A4 5 32 A15 Logic block diagram CE 6 31 OE I/O1 7 30 I/O8 I/O2 8 29 I/O7 V 9 28 GND CC V GND 10 27 CC V CC I/O3 11 26 I/O6 I/O4 12 25 I/O5 GND WE 13 24 A14 A5 14 23 A13 Input buffer A6 15 22 A12 A7 16 21 A11 A8 17 20 A10 A0 A9 18 19 NC A1 I/O1 A2 524,288 8 A3 A4 Array 44-pin TSOP 2 A5 (4,194,304) NC NC A6 1 44 NC NC A7 2 43 I/O8 A0 NC 3 42 A8 A18 A1 4 41 A9 A2 5 40 A17 A3 A16 6 39 A4 7 38 A15 Column decoder WE Control CE 8 37 OE OE I/O1 9 36 I/O8 Circuit CE I/O2 I/O7 10 35 V 11 34 GND CC V GND 12 33 CC I/O3 13 32 I/O6 I/O4 14 31 I/O5 WE A14 15 30 A5 16 29 A13 A6 17 28 A12 A7 A11 18 27 A8 19 26 A10 A9 NC 20 25 NC NC 21 24 NC 22 23 NC Selection guide 10 12 15 20 Unit Maximum address access time 10 12 15 20 ns Maximum outputenable access time 4 5 6 7 ns Industrial 180 160 140 110 mA Maximum operating current Commercial 170 150 130 100 mA Maximum CMOS standby current 8 8 8 8 mA 8/17/04, v. 2.1 Alliance Semiconductor P. 1 of 9 Copyright Alliance Semiconductor. All rights reserved. Row decoder A10 A11 A12 A13 A14 A15 A16 A17 A18 Sense ampAS7C34096A Functional description The AS7C34096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 4/5/6/7 ns are AA RC WC OE ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.5 +5.0 V CC t1 Voltage on any pin relative to GND V 0.5 V +0.5 V t2 CC Power dissipation P 1.0 W D Storage temperature (plastic) T 65 +150 C stg Temperature with V applied T 55 +125 C CC bias DC current into output (low) I 20 mA OUT NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode Standby (I , I ) H X X High Z SB SB1 Output disable (I ) L H H High Z CC D Read (I ) LH L OUT CC D Write (I ) LL X IN CC Key: X = Dont care, L = Low, H = High 8/17/04, v. 2.1 Alliance Semiconductor P. 2 of 9