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AS4C64M16D3LA-12BIN

AS4C64M16D3LA-12BIN electronic component of Alliance Memory

Datasheet
DRAM 1G 1.35V 800MHz 64M x 16 DDR3
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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N/A

Obsolete

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0 - WHS 1

MOQ : 1
Multiples : 1

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AS4C64M16D3LA-12BIN
Alliance Memory

1 : USD 9.4737
10 : USD 6.6566
25 : USD 6.5351
50 : USD 6.485
100 : USD 5.876
250 : USD 5.863
500 : USD 5.72
1000 : USD 5.629
2000 : USD 5.46
N/A

Obsolete

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Additional Infomation About Product

AS4C64M16D3LA-12BIN AS4C64M16D3LA-12BCN Revision History AS4C64M16D3LA-12BCN/AS4C64M16D3LA-12BIN 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Aug. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/85 - Rev.1.0 Aug 2016AS4C64M16D3LA-12BIN AS4C64M16D3LA-12BCN Features Overview JEDEC Standard Compliant The 1Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = 1.5V 0.075V DD DDQ DRAM. Industrial temperature The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank Commercial: 0C to 95C (TC) devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin Industrial :-40C to 95C (TC) for general applications. Supports JEDEC clock jitter specification The chip is designed to comply with all key DDR3L Fully synchronous operation DRAM key features and all of the control and address Fast clock rate: 800 MHz inputs are synchronized with a pair of externally supplied Differential Clock, CK & CK differential clocks. Inputs are latched at the cross point Bidirectional differential data strobe of differential clocks (CK rising and CK falling). All - DQS & DQS I/Os are synchronized with differential DQS pair in a source synchronous fashion. 8 internal banks for concurrent operation These devices operate with a single 1.35V -0.067V 8n-bit prefetch architecture /+0.1V power supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8 s -40C TC +85C 3.9 s +85C TC +95C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 8 x 13 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Org Max Clock (MHz) Product part No Package 800 AS4C64M16D3LA-12BCN 64M x 16 Commercial 0C to 95C 96-ball FBGA 800 AS4C64M16D3LA-12BIN 64M x 16 Industrial -40C to 95C 96-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 800 MHz 11 13.75 13.75 DDR3 L-1600 Confidential - 2/85 - Rev.1.0 Aug 2016

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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