Product Information

AS4C64M16D1-6TCN

AS4C64M16D1-6TCN electronic component of Alliance Memory

Datasheet
DRAM 1GB, 2.5V, 166Mhz 64M x 16 DDR1
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 29.2572 ea
Line Total: USD 29.26

190 - Global Stock
Ships to you between
Mon. 27 May to Wed. 29 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
140 - WHS 1


Ships to you between Mon. 27 May to Wed. 29 May

MOQ : 1
Multiples : 1

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AS4C64M16D1-6TCN
Alliance Memory

1 : USD 24.518
10 : USD 23.2185
25 : USD 22.655
50 : USD 22.6435
108 : USD 20.2055
216 : USD 19.665
540 : USD 19.665
1080 : USD 19.435
2592 : USD 19.0095

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Additional Infomation About Product

AS4C64M16D1 Revision History AS4C64M16D1 66-pin TSOP II package Revision Details Date Rev 1.0 Preliminary datasheet Sep 2014 Rev 2 Speed grade option changed -5(400MHz) to -6(333MHz) Oct 2014 Confidential 1 Rev. 2.0 Oct. /2014 AS4C64M16D1 64M x 16 bit DDR1 Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 2.0, Oct. /2014) Features Description High speed data transfer rates with system The AS4C64M16D1 is a four bank DDR DRAM frequency up to 200MHz organized as 4 banks x 16Mbit x 16. The - Data Mask for Write Control AS4C64M16D1 achieves high speed data transfer - Four Banks controlled by BA0 & BA1 rates by employing a chip architecture that - Programmable CAS Latency: 2, 2.5, 3 prefetches multiple bits and then synchronizes the - Programmable Wrap Sequence: output data to a system clock. Sequential or Interleave All of the controls, address, circuits are - Programmable Burst synchronized with the positive edge of an externally Length: 2, 4, 8 for supplied clock. I/O transactions are occurring on Sequential Type 2, 4, 8 both edges of DQS. for Interleave Type Operating the four memory banks in an - Automatic and Controlled Precharge Command interleaved fashion allows random access operation - Power Down Mode to occur at a higher rate than is possible with - Auto Refresh and Self Refresh standard DRAMs. A sequential and gapless data - Refresh Interval: 8192 cycles/64 ms rate is possible depending on burst length, CAS - Available in 66 Pin TSOP II - SSTL-2 Compatible I/Os latency and speed grade of the device. - Double Data Rate (DDR) - Bidirectional Data Strobe (DQS) for input and output data, active on both edges -6 - On-Chip DLL aligns DQ and DQs transitions with DDR333 CK transitions - CK Clock Cycle Time (t ) 7.5ns CK2 - VDD = 2.5V 0.2V, VDDQ = 2.5V 0.2V Clock Cycle Time (t ) 6ns CK2.5 VDD = 2.6V 0.1V, VDDQ = 2.6V 0.1V (DDR400) Clock Cycle Time (t ) 6ns CK3 - tRAS lockout supported System Frequency (f ) CK max 166 MHz - Concurrent auto precharge option is supported All parts are ROHS compliant Table 1. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR1-333 166 MHz 3 18 18 Table 2. Ordering Information Product part No Org Temperature Package AS4C64M16D1-6TCN 64M x 16 Commercial 66-pin TSOP II 0C to 70C AS4C64M16D1-6TIN 64M x 16 Industrial 66-pin TSOP II -40C to 85C Confidential 2 Rev. 2.0 Oct. /2014

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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