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AS4C512M8D3LB-12BIN

AS4C512M8D3LB-12BIN electronic component of Alliance Memory

Datasheet
DRAM 4G 1.35V 800MHz 512M x 8 DDR3 I-Temp
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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N/A

Obsolete

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0 - WHS 1

MOQ : 1
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AS4C512M8D3LB-12BIN
Alliance Memory

1 : USD 14.1515
10 : USD 12.7279
25 : USD 12.4345
50 : USD 12.3668
100 : USD 11.3738
220 : USD 10.8097
440 : USD 10.6968
1100 : USD 10.5389
N/A

Obsolete

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Additional Infomation About Product

AS4C512M8D3LB Revision History 4Gb DDR3L AS4C512M8D3LB 78ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Dec. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 47 - Rev.1.0. Dec. 2017AS4C512M8D3LB HIGH PERFORMANCE 4Gbit DDR3L SDRAM Specifications Features - Density : 4G bits - Double-data-rate architecture two data transfers per clock cycle - Organization : - The high-speed data transfer is realized by the 8 bits prefetch pipe- - 64M words x 8 bits x 8 banks lined architecture - Package : - Bi-directional differential data strobe (DQS and DQS ) is transmitted/ - 78-ball FBGA received with data for capturing data at the receiver - Lead-free (RoHS compliant) and Halogen-free - DQS is edge-aligned with data for READs center-aligned with data - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) for WRITEs - Backward compatible to VDD, VDDQ = 1.5V 0.075V - Differential clock inputs (CK and CK) - Data rate : 1600Mbps - DLL aligns DQ and DQS transitions with CK transitions - 1KB page size - Commands entered on each positive CK edge data and data mask - Row address: A0 to A15 referenced to both edges of DQS - Column address: A0 to A9 ( 512Mb x 8) - Data mask (DM) for write data - Eight internal banks for concurrent operation - Posted CAS by programmable additive latency for better command - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) and data bus efficiency - Burst type (BT) : - On-Die Termination (ODT) for better signal quality - Sequential (8, 4 with BC) - Synchronous ODT - Interleave (8, 4 with BC) - Dynamic ODT - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11, 13 - Asynchronous ODT - CAS Write Latency (CWL) : 5, 6, 7, 8 ,9 - Multi Purpose Register (MPR) for pre-defined pattern read out - Precharge : auto precharge option for each burst access - ZQ calibration for DQ drive and ODT - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - Programmable Partial Array Self-Refresh (PASR) - Refresh : auto-refresh, self-refresh - RESET pin for Power-up sequence and reset function - Refresh cycles : - SRT range : Normal/extended - Average refresh period - Programmable Output driver impedance control 7.8 s at -4 0C Tc +85C 3.9 s at +85C < Tc +105C - Operating case temperature range - Commercial Tc = 0C to +95C - Industrial Tc = -40C to +95C - Automotive Tc = -40C to +105C Table 1. Ordering Information Product Part No. Org. Temperature Max Clock (MHz) Package AS4C512M8D3LB-12BCN 512M x 8 0C to 95C 800 78-ball FBGA AS4C512M8D3LB-12BIN 512M x 8 -40C to 95C 800 78-ball FBGA AS4C512M8D3LB-12BAN 512M x 8 -40C to 105C 800 78-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3 L-1600 Confidential - 2 of 47 - Rev.1.0. Dec. 2017

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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