AS4C4M16SA-6BINTR

AS4C4M16SA-C&I Revision History Revision Details Date Rev 1.0 Preliminary datasheet. June 2013 Rev 2.0 Modify some typing errors. March 2014 Rev 3.0 Add AS4C4M16SA-6TCN part. March 2015 Rev 4.0 Add AS4C4M16SA-7B2CN 60-ball package and Part Number. March 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Confidential - 1 of 56 - Rev.4.0 March 2017AS4C4M16SA-C&I 64M (4M x 16 bit) Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 3.0, Mar. /2015) Features Overview Fast access time from clock: 5.4/5.4 ns The 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally Fast clock rate: 166/143 MHz configured as 4 Banks of 1M word x 16 DRAM with a Fully synchronous operation synchronous interface (all signals are registered on Internal pipelined architecture the positive edge of the clock signal, CLK). Read and 1M word x 16-bit x 4-bank write accesses to the SDRAM are burst oriented Programmable Mode registers accesses start at a selected location and continue for - CAS Latency: 2 or 3 a programmed number of locations in a programmed - Burst Length: 1, 2, 4, 8, or full page sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a - Burst Type: Sequential or Interleaved Read or Write command. - Burst stop function The SDRAM provides for programmable Read or - Optional drive strength control Write burst lengths of 1, 2, 4, 8, or full page, with a Operating temperature range burst termination option. An auto precharge function - Commercial (0 ~ 70C) may be enabled to provide a self-timed row precharge - Industrial (-40 ~ 85C) that is initiated at the end of the burst sequence. The Auto Refresh and Self Refresh refresh functions, either Auto or Self Refresh are easy 4096 refresh cycles/64ms to use. By having a programmable mode register, the CKE power down mode system can choose the most suitable modes to maximize its performance. These devices are well Single +3.3V 0.3V power supply suited for applications requiring high memory Interface: LVTTL bandwidth and particularly well suited to high 54-pin 400 mil plastic TSOP II package performance PC applications. 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package 60-ball 6.4 x 10.1 x 1.0mm FBGA package - All parts ROHS Compliant Table 1. Key Specifications AS4C4M16S -6/7 tCK3 Clock Cycle time(min.) 6/7 ns tAC3 Access time from CLK (max.) 5.4/5.4 ns tRAS Row Active time(min.) 42/42 ns tRC Row Cycle time(min.) 60/63 ns Table 2.Ordering Information Part Number Frequency Package Temperature Temp Range AS4C4M16SA-6BIN 166MHz 54-Ball FBGA Industrial -40 ~ 85C AS4C4M16SA-7BCN 143MHz 54-Ball FBGA Commercial 0 ~ 70C AS4C4M16SA-6TIN 166MHz 54-Pin TSOPII Industrial -40 ~ 85C AS4C4M16SA-7TCN 143MHz 54-Pin TSOPII Commercial 0 ~ 70C AS4C4M16SA-6TCN 166MHz 54-Pin TSOPII Commercial 0 ~ 70C AS4C4M16SA-7B2CN 143MHz 60-Ball FBGA Commercial 0 ~ 70C B: indicates FBGA package B2: indicates a second FBGA package option T: indicates TSOP II package N: indicates Pb and Halogen Free Confidential - 2 of 56 - Rev.4.0 March 2017