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AS4C256M16D4-83BINTR

AS4C256M16D4-83BINTR electronic component of Alliance Memory

Datasheet
DRAM
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2500: USD 10.4434 ea
Line Total: USD 26108.5

0 - Global Stock
MOQ: 2500  Multiples: 2500
Pack Size: 2500

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0 - WHS 1


Ships to you between Fri. 17 May to Tue. 21 May

MOQ : 2500
Multiples : 2500

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AS4C256M16D4-83BINTR
Alliance Memory

2500 : USD 9.154
5000 : USD 8.9815

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Additional Infomation About Product

AS4C256M16D4 Revision History 4Gb DDR4 AS4C256M16D4 - 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Aug 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 201 - Rev.1.0 Aug.2019AS4C256M16D4 256M x 16 bit DDR4 Synchronous DRAM (SDRAM) Advance (Rev. 1. 0, Aug. /2019) Features JEDEC Standard Compliant Internal V Training REFDQ Fast clock rate: 1200/1333MHz Read Preamble Training Power supplies: Control Gear Down Mode - V & V = +1.2V 0.06V DD DDQ Per DRAM Addressability (PDA) - V = +2.5V -0.125V / +0.25V PP Output Driver Impedance Control Operating temperature range: Dynamic on-die termination (ODT) - Commercial : T = 0~95 C C Input Data Mask (DM) and Data Bus Inversion (DBI) - Industrial: T = -40~95 C C ZQ Calibration Supports JEDEC clock jitter specification Command/Address latency (CAL) Bidirectional differential data strobe, DQS &DQS Asynchronous Reset Differential Clock, CK & CK DLL enable/disable 8 internal banks: 2 groups of 4 banks each Burst Length (BL8/BC4/BC4 or 8 on the fly) Separated IO gating structures by Bank Group Burst type: Sequential / Interleave 8n-bit prefetch architecture CAS Latency (CL) Precharge & Active power down CAS Write Latency (CWL) Auto Refresh and Self Refresh Additive Latency (AL): 0, CL-1, CL-2 Low-power auto self refresh (LPASR) Average refresh period Self Refresh Abort - 8192 cycles/64ms (7.8us at -40C TC +85C) Fine Granularity Refresh - 8192 cycles/32ms (3.9us at +85C T +95C) C Dynamic ODT (RTT PARK & RTT Nom & RTT WR) Data Interface: Pseudo Open Drain (POD) Write Leveling RoHS compliant DQ Training via MPR Hard post package repair (hPPR) Programmable preamble is supported both of 1t CK Soft post package repair (sPPR) and 2t mode CK Package: Pb Free and Halogen Free Command/Address (CA) Parity - 96-ball 7.5 x 13.5 x 1.2mm FBGA Data bus write cyclic redundancy check (CRC) Boundary Scan Mode Table 1. Ordering Information Product part No Org Temperature Max Clock (MHz) Package Commercial (Extended) 96-ball FBGA AS4C256M16D4-83BCN 256M x 16 1200 0C to 95C AS4C256M16D4- 83BIN Industrial -40C to 95C 96-ball FBGA 256M x 16 1200 Commercial (Extended) AS4C256M16D4- 75BCN 256M x 16 96-ball FBGA 1333 0C to 95C AS4C256M16D4-75B IN Industrial -40C to 95C 96-ball FBGA 256M x 16 1333 Table 2. Speed Grade Information CAS Latency tRCD(ns) Speed Grade Clock Frequency tRP(ns) DDR4-2400 1200 MHz 17 14.16 14.16 DDR4-2666 1333 MHz 19 14.25 14.25 Confidential - 2 of 201 - Rev.1.0 Aug.2019

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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