Product Information

AS4C1G8D3LA-10BCN

AS4C1G8D3LA-10BCN electronic component of Alliance Memory

Datasheet
DRAM 8G 1Gx8 933MHz 1.35V DDR3 ET
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 28.9455 ea
Line Total: USD 28.95

331 - Global Stock
Ships to you between
Fri. 24 May to Tue. 28 May
MOQ: 1  Multiples: 1
Pack Size: 1

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234 - WHS 1


Ships to you between Fri. 24 May to Tue. 28 May

MOQ : 1
Multiples : 1

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AS4C1G8D3LA-10BCN
Alliance Memory

1 : USD 28.9455
10 : USD 27.2205
25 : USD 26.5535
50 : USD 25.7255
100 : USD 23.1725
220 : USD 23.1725
440 : USD 23.1725
1100 : USD 22.402
2640 : USD 22.2755

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Additional Infomation About Product

AS4C1G8D3LA Revision History 8Gbit DDR3L SDRAM 8 BANKS X 128Mbit X 8 - Dual Die Package (DDP) 78ball FBGA Package Revision Details Date Rev 1.0 Preliminary datasheet Feb. 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Rev.1.0. Feb.2019 Confidential - 1 of 41 -AS4C1G8D3LA Specifications - Density : 8G bits Features - Organization : - Double-data-rate architecture two data transfers per clock cycle - 128M words x 8 bits x 8 banks - The high-speed data transfer is realized by the 8 bits prefetch pipe- - Package : lined architecture - 78-ball FBGA - Bi-directional differential data strobe (DQS and DQS) is transmitted/ - Two 1Gbit x 4 dies stacked (DDP) received with data for capturing data at the receiver - Lead-free (RoHS compliant) and Halogen-free - DQS is edge-aligned with data for READs center-aligned with data - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) for WRITEs - -Backward compatible to VDD, VDDQ = 1.5V 0.075V - Differential clock inputs (CK and CK) - Data rate : 1866Mbps - DLL aligns DQ and DQS transitions with CK transitions - 2KB page size - Commands entered on each positive CK edge data and data mask - Row address: A0 to A15 referenced to both edges of DQS - Column address: A0 to A9, A11 - Data mask (DM) for write data - Eight internal banks for concurrent operation - Posted CAS by programmable additive latency for better command - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) and data bus efficiency - Burst type (BT) : - On-Die Termination (ODT) for better signal quality - Sequential (8, 4 with BC) - Synchronous ODT - Interleave (8, 4 with BC) ODT - Dynamic - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11, 13 - Asynchronous ODT - CAS Write Latency (CWL) : 5, 6, 7, 8 ,9 - Multi Purpose Register (MPR) for pre-defined pattern read out - Precharge : auto precharge option for each burst access - ZQ calibration for DQ drive and ODT - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - RESET pin for Power-up sequence and reset function - Refresh : auto-refresh, self-refresh - SRT range : Normal/extended - Refresh cycles : - Programmable Output driver impedance control - Average refresh period 7.8 s at -40C Tc +85C 3.9 s at +85C < Tc +105C - Operating case temperature range - Commerc ial Tc = 0C to +95C - Industrial Tc = -40C to +95C - Automotive Tc = -40C to +105C Table 1. Ordering Information Org Temperature Max Clock (MHz) Product part No Package 933 AS4C1AS4C1G8D3LA-10BCNG8D3LA-10BCN 78-ball FBGA 1G x 8 Commercial 0C to 95C 933 AS4C1G8D3LA-10BIN 1G x 8 Industrial -40C to 95C 78-ball FBGA 933 78-ball FBGA 1G x 8 Automotive -40C to 105C AS4C1G8D3LA-10BAN Table 2. Speed Grade Information CAS Latency tRCD(ns) Speed Grade Clock Frequency tRP(ns) DDR3-1866 933 MHz 13 13.91 13.91 - 2 of 41 - Rev.1.0. Feb.2019

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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