Product Information

AS4C128M32MD4-062BAN

AS4C128M32MD4-062BAN electronic component of Alliance Memory

Datasheet
SDRAM - Mobile LPDDR4 Memory IC 4Gb (128M x 32) LVSTL 1.6GHz 3.5ns 200-FBGA (10x14.5)
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 25.137 ea
Line Total: USD 25.14

572 - Global Stock
Ships to you between
Tue. 28 May to Thu. 30 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
393 - WHS 1


Ships to you between Tue. 28 May to Thu. 30 May

MOQ : 1
Multiples : 1

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AS4C128M32MD4-062BAN
Alliance Memory

1 : USD 23.6785
10 : USD 22.057
25 : USD 21.8155
50 : USD 21.2865
100 : USD 19.067
272 : USD 19.0555
544 : USD 18.4115
1088 : USD 18.1815
2584 : USD 18.124

Read More Specifications

     
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Additional Infomation About Product

2Gb/4Gb/8Gb LPDDR4 Revision History For 2Gb/4Gb/8Gb LPDDR4 200ball FBGA Package Revision Details Date Rev 1.0 Initial Release Aug 2020 Confidential - 1 of 64 - Rev. 1.0 Aug. 2020 2Gb/4Gb/8Gb LPDDR4 1 Overview The LPDDR4 SDRAM is organized as 1 or 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. 1.1 Features The 2Gb/4Gb/8Gb LPDDR4 SDRAM offers the Bidirectional/differential data strobe per byte of data following key features: (DQS, DQS) Configuration: DMI pin support for write data masking and DBI - x32 for 2-channels per device (AS4C64M32MD4 , functionality AS4C128M32MD4, AS4C256M32MD4) Programmable READ and WRITE latencies (RL/WL) - x16 for 1-channel per device Programmable and on-the-fly burst lengths (BL =16, (AS4C128M16MD4, AS4C256M16MD4) 32) - 8 internal banks per each channel Support non-targert DRAM ODT control On-Chip ECC: Directed per-bank refresh for concurrent bank - Single-bit error correction (per 64-bits), which will operation and ease of command scheduling maximize reliability ZQ Calibration - Optional ERR output signal per channel, which Operation Temperature: indicates ECC event occurrence C - ECC Register, which controls ECC function - Automotive A2 (TC = -40C to 105 Low-voltage Core and I/O Power Supplies: On-chip temperature sensor to control self refresh rate - VDD2 /VDDQ = 1.06-1.17V, VDD1 = 1.70-1.95V On-chip temperature sensor whose status can be LVSTL(Low Voltage Swing Terminated Logic) I/O read from MR4 Interface RoHS-compliant, green packaging Internal VREF and VREF Training Package: Dynamic ODT : 2Gb/4Gb : 200 ball FBGA (10mm x 14.5mm x 0.8mm) - DQ ODT :VSSQ Termination 8Gb : 200 ball FBGA (10mm x 14.5mm x 1.1mm) - CA ODT :VSS Termination Selectable output drive strength (DS) Max. Clock Frequency : 1.6GHz (3.2Gbps for one channel) 16-bit Pre-fetch DDR data bus Single data rate (multiple cycles) command/address bus Table 1. Speed Grade Information Speed Grade Clock Frequency RL t CK (ns) DDR4L-3200 1600MHz 28 0 .625 *Other clock frequencies/data rates supported please refer to AC timing tables Confidential - 2 of 64 - Rev. 1.0 Aug. 2020

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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