AS4C128M16D3LC-12BCN

AS4C128M16D2A-25BAN Revision History 128M x 16 DDR2 Automotive - 84-ball FBGA Package Revision Details Date Rev 1.0 Preliminary datasheet Dec. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 63 - Rev.1.0 Dec. 2018AS4C128M16D2A-25BAN 128M x 16 bit DDRII Synchronous DRAM (SDRAM) Automotive (Rev. 1.0, Dec. /2018) Features Overview JEDEC Standard Compliant The 2Gb DDR2 is a high-speed CMOS Double-Data- Rate-Two (DDR2), synchronous dynamic random- JEDEC Standard 1.8V I/O (SSTL 18-compatible) access memory (SDRAM) containing 2048 Mbits in a AEC-Q100 Compliant 16-bit wide data I/Os. It is internally configured as a Power supplies: V & V = +1.8V 0.1V DD DDQ eight bank DRAM, 8 banks x 16Mb addresses x 16 I/Os. Operating temperature: T = -40~105 C (Automotive) C The device is designed to comply with DDR2 DRAM Supports JEDEC clock jitter specification key features such as posted CAS with additive latency, Fully synchronous operation Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination(ODT). Fast clock rate: 400MHz All of the control and address inputs are synchronized Differential Clock, CK & CK with a pair of externally supplied differential clocks. Inputs Bidirectional single/differential data strobe are latched at the cross point of differential clocks (CK - DQS & DQS rising and CK falling). All I/Os are synchronized with a 8 internal banks for concurrent operation pair of bidirectional strobes (DQS and DQS ) in a source 4-bit prefetch architecture synchronous fashion. The address bus is used to convey Internal pipeline architecture row, column, and bank address information in RAS , CAS multiplexing style. Accesses begin with the registration Precharge & active power down of a Bank Activate command, and then it is followed by Programmable Mode & Extended Mode registers a Read or Write command. Read and write accesses to Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5, 6 the DDR2 SDRAM are 4 or 8-bit burst oriented accesses WRITE latency = READ latency - 1 t CK start at a selected location and continue for a programmed Burst lengths: 4 or 8 number of locations in a programmed sequence. Operating Burst type: Sequential / Interleave the four memory banks in an interleaved fashion allows DLL enable/disable random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge Off-Chip Driver (OCD) function may be enabled to provide a self-timed row - Impedance Adjustment precharge that is initiated at the end of the burst sequence. - Adjustable data-output drive strength A sequential and gapless data rate is possible depending On-die termination (ODT) on burst length, CAS latency, and speed grade of the RoHS compliant device. Auto Refresh and Self Refresh - Not Support self refresh function with T > 95C C Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/16ms (1.95us at +85C T +105C) C 84-ball 8x12.5x1.2mm (max) FBGA - Pb and Halogen Free Table 1. Speed Grade Information tRCD(ns) Speed Grade Clock Frequency CAS Latency tRP(ns) 12.5 12.5 DDR2-800 400MHz 5 Table 2. Ordering Information Org Temperature Max Clock (MHz) Product part No Package AS4C128M16D2A-25B AN 400 84-ball FBGA 128Mx 16 Automotive -40C to 105C Confidential - 2 of 63 - Rev.1.0 Dec. 2018