Product Information

AS4C128M16D3LB-12BCNTR

AS4C128M16D3LB-12BCNTR electronic component of Alliance Memory

Datasheet
AS4C128M16D3LB Series 2 Gb (128 M x 16) 1.35 V 800 MHz DDR3 SDRAM - FBGA-96
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1

MOQ : 2000
Multiples : 2000

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AS4C128M16D3LB-12BCNTR
Alliance Memory

2000 : USD 4.1698
N/A

Obsolete
0 - WHS 2

MOQ : 2000
Multiples : 2000

Stock Image

AS4C128M16D3LB-12BCNTR
Alliance Memory

2000 : USD 5.2635
N/A

Obsolete

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Additional Infomation About Product

AS4C128M16D3LB-12BCN Revision History 2Gb AS4C128M16D3LB-12BCN - 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Mar. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/45 - Rev.1.0 Mar 2016AS4C128M16D3LB-12BCN Specifications Features - Density : 2G bits - Double-data-rate architecture two data transfers per clock cycle - Organization : - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - 16M words x 16 bits x 8 banks - Bi-directional differential data strobe (DQS and DQS) is transmitted/ - Package : received with data for capturing data at the receiver - 96-ball FBGA - DQS is edge-aligned with data for READs center-aligned with data - Lead-free (RoHS compliant) and Halogen-free for WRITEs - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) - Differential clock inputs (CK and CK) - Backward compatible to VDD, VDDQ = 1.5V 0.075V - DLL aligns DQ and DQS transitions with CK transitions - Data rate : 1600Mbps - Commands entered on each positive CK edge data and data mask - 2KB page size referenced to both edges of DQS - Row address: A0 to A13 - Data mask (DM) for write data - Column address: A0 to A9 - Posted CAS by programmable additive latency for better command and data bus efficiency - Eight internal banks for concurrent operation - On-Die Termination (ODT) for better signal quality - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) - Synchronous ODT - Burst type (BT) : - Dynamic ODT - Sequential (8, 4 with BC) - Asynchronous ODT - Interleave (8, 4 with BC) - Multi Purpose Register (MPR) for pre-defined pattern read out - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11 - ZQ calibration for DQ drive and ODT - CAS Write Latency (CWL) : 5, 6, 7, 8 - RESET pin for Power-up sequence and reset function - Precharge : auto precharge option for each burst access - SRT range : Normal/extended - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - Programmable Output driver impedance control - Refresh : auto-refresh, self-refresh - Refresh cycles : - Average refresh period 7.8 s at 0C Tc +85C 3.9 s at +85C < Tc +95C - Operating case temperature range - Comercial Tc = 0C to +95C Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package Commercial (Extended) 800 96-ball FBGA AS4C128M16D3 LB-12BCN 128Mx16 0C to 95C Table 2. Speed Grade Information tRP (ns) Speed Grade Clock Frequency CAS Latency tRCD (ns) DDR3L-1600 800MHz 1 1 1 3.75 1 3.75 Confidential - 2/45 - Rev.1.0 Mar 2016

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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