EMK31 Series REGULATORY COMPLIANCE 2011/65 + 191 SVHC 2015/863 ITEM DESCRIPTION MEMS Clock Oscillators LVCMOS (CMOS) 1.8Vdc 4 Pad 2.5mm x 3.2mm Plastic Surface Mount (SMD) ELECTRICAL SPECIFICATIONS Nominal Frequency 1MHz to 125MHz Frequency Tolerance/Stability Inclusive of all conditions: Calibration Tolerance at 25C, Frequency Stability over the Operating Temperature Range, Supply Voltage Change, and Output Load Change 100ppm Maximum over 0C to +70C 50ppm Maximum over 0C to +70C 25ppm Maximum over 0C to +70C 20ppm Maximum over 0C to +70C 100ppm Maximum over -20C to +70C 50ppm Maximum over -20C to +70C 25ppm Maximum over -20C to +70C 20ppm Maximum over -20C to +70C 100ppm Maximum over -40C to +85C 50ppm Maximum over -40C to +85C 25ppm Maximum over -40C to +85C 20ppm Maximum over -40C to +85C Aging at 25C 1.5ppm Maximum First Year Supply Voltage 1.8Vdc 10% Input Current No Load 4.5mA Maximum over Nominal Frequency of 1MHz to 20MHz 5mA Maximum over Nominal Frequency of 20.000001MHz to 50MHz 6mA Maximum over Nominal Frequency of 50.000001MHz to 80MHz 7mA Maximum over Nominal Frequency of 80.000001MHz to 125MHz Output Voltage Logic High (V ) IOH = -2mA Oh 90% of Vdd Minimum Output Voltage Logic Low (V ) IOL = +2mA Ol 10% of Vdd Maximum Rise/Fall Time Measured from 20% to 80% of waveform 1.5nSec Typical, 3.5nSec Maximum Duty Cycle Measured at 50% of waveform 50 10(%) 50 5(%) Load Drive Capability 15pF Maximum Output Logic Type CMOS Output Control Function Tri-State (Disabled Output: High Impedance) Power Down (Disabled Output: Logic Low) Output Control Input Voltage Logic 70% of Vdd Minimum or No Connect to Enable Output High (Vih) Output Control Input Voltage Logic 30% of Vdd Maximum to Disable Output Low (Vil) Power Down Output Enable Time 5mSec Maximum (Disabled Output: Logic Low) Tri-State Output Enable Time 150nSec Maximum (Disabled Output: High Impedance) Power Down Output Disable Time 150nSec Maximum (Disabled Output: Logic Low) Tri-State Output Disable Time 150nSec Maximum (Disabled Output: High Impedance) Standby Current 5A Maximum (Disabled Output: Logic Low) Period Jitter (RMS) 2pSec Typical, 5pSec Maximum RMS Phase Jitter (Fj = 900kHz to 0.5pSec Typical, 1pSec Maximum 7.5MHz Random) Revised M: 8/19/2020 Page 1 of 8 www.ecliptek.com NRNDEMK31 Series 1.5pSec Typical, 3pSec Maximum RMS Phase Jitter (Fj = 12kHz to 20MHz Random) Start Up Time 5mSec Maximum Storage Temperature Range -65C to +150C PART NUMBERING GUIDE Revised M: 8/19/2020 Page 2 of 8 www.ecliptek.com NRND