74LVC1G32GV-Q100H

74LVC1G32-Q100 Single 2-input OR gate Rev. 5 18 May 2021 Product data sheet 1. General description The 74LVC1G32-Q100 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I OFF OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation I circuitry provides partial Power-down mode operation OFF 24 mA output drive (V = 3.0 V) CC Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G32GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74LVC1G32GV-Q100 -40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74LVC1G32GM-Q100 -40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mmNexperia 74LVC1G32-Q100 Single 2-input OR gate 4. Marking Table 2. Marking Type number Marking code 1 74LVC1G32GW-Q100 VG 74LVC1G32GV-Q100 V32 74LVC1G32GM-Q100 VG 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B 1 B 1 1 Y 4 4 Y 2 A 2 A mna164 mna165 mna166 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G32 74LVC1G32 B 1 6 V CC B 1 5 V CC A 2 5 n.c. A 2 GND 3 4 Y 3 4 GND Y 001aab641 001aab640 Transparent top view Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) Fig. 5. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description TSSOP5 and SC-74A XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected V 5 6 supply voltage CC 74LVC1G32 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 18 May 2021 2 / 12