LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI DS205 October 16, 2012 Product Specification v3.167 & v4.18 Features LogiCORE IP Facts Fully compatible 64-bit, 66/33 MHz LogiCORE Core Specifics IP Initiator/Target core for PCI Supported Device See Table 1. (1) Customizable, programmable, single-chip solution Family Resource v4 Core v3 Core Pre-defined implementation for predictable timing (2) Utilization Incorporates Xilinx Smart-IP technology LUTs 565 724 3.3V operation at 066 MHz Slice Flip-Flops 404 732 5.0V operation at 033 MHz IOB Flip-Flops 94 176 Fully verified design tested with Xilinx proprietary IOBs 94 89 test bench and hardware (3) GCLK 2 1 Delivered through Xilinx CORE Generator tool and Vivado IP Catalog Provided with Core CardBus compliant Product Specification v3 & v4 Getting Started Guide v3 Supported initiator functions: Documentation User Guide v4 User Guide v3 Configuration read, configuration write ISE: VHDL/Verilog Simulation Model Memory read, memory write, MRM, MRL ISE: NGC Netlist (v4 core only) Design File Formats Interrupt acknowledge, special cycles ISE: NGO Netlist (v3 core only) Vivado: Encrypted RTL I/O read, I/O write ISE: UCF Supported target functions: Constraints File Vivado: XDC Type 0 configuration space header Test Bench VHDL/Verilog Example Test Bench Up to three base address registers (MEM or Instantiation Template VHDL/Verilog Wrapper I/O with adjustable block size from 16 bytes to Example Designs VHDL/Verilog Example Design 2 GB) (4) Tested Design Flows Medium decode speed ISE Design Suite v14.3 Parity generation, parity error detection Design Entry (5) Vivado Design Suite v2012.3 Configuration read, configuration write Mentor Graphics ModelSim Memory read, memory write, MRM, MRL Simulation Cadence Incisive Enterprise Simulator (IES) Interrupt acknowledge Xilinx XST Synthesis I/O read, I/O write Vivado Synthesis Target abort, target retry, target disconnect Support Provided by Xilinx www.xilinx.com/support 1. For a complete listing of supported devices, see the release notes for this core. 2. Resource utilization depends on core configuration and design requirements. Unused resources are trimmed by the Xilinx technology mapper. Utilization figures reported represent a maximum configuration. 3. Designs running at 66 MHz in Virtex -4 and Virtex-5 FPGA imple- mentations require additional BUFG for 200 MHz reference clock. 4. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. 5. Supports 7 series devices only. Copyright 20102012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS205 October 16, 2012 www.xilinx.com 1 Product Specification v3.167 & v4.18LogiCORE IP 64-Bit Initiator/Target v3 & v4 for PCI Xilinx provides technical support for this LogiCORE IP product when used as described. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if customized beyond that described in the related product documentation. For Spartan -6 devices, only those devices listed in Table 1 have been tested with the latest software speed files to meet PCI timing. For a part or package not listed in the data sheet, open a WebCase with Xilinx for latest available status. Table 1: Core Implementation (1),(2) Supported Device Core Version Signaling Environment PCI64/66 (3) Virtex-5 XC5VFX70T-FF1136-2C/I (regional clock) v4 3.3V only (3) Virtex-5 XC5VLX50-FF1153-2C/I (regional clock) v4 3.3V only (3) Virtex-5 XC5VLX50T-FF1136-2C/I (regional clock) v4 3.3V only (3) Virtex-5 XC5VLX110-FF1153-2C/I (regional clock) v4 3.3V only (3) Virtex-5 XC5VLX110T-FF1136-2C/I (regional clock) v4 3.3V only (3) Virtex-5 XC5VSX50T-FF1136-2C/I (regional clock) v4 3.3V only (3) Virtex-5 XC5VSX95T-FF1136-2C/I (regional clock) v4 3.3V only (3) Virtex-4 XC4VFX20-FF672-11C/I (regional clock) v3 3.3V only (3),(4) Virtex-4 XC4VLX25-FF668-11C/I (regional clock) v3 3.3V only (3),(4) Virtex-4 XC4VSX35-FF668-11C/I (regional clock) v3 3.3V only Spartan-3A XC3S400A-FG400-5C v3 3.3V only Spartan-3A XC3S700A-FG400-5C v3 3.3V only Spartan-3A XC3S700A-FG484-5C v3 3.3V only Spartan-3A XC3S1400A-FG484-5C v3 3.3V only Spartan-3A XC3S1400A-FG676-5C v3 3.3V only Spartan-3ADSP XC3SD1800A-FG676-5C v3 3.3V only Spartan-3ADSP XC3SD3400A-FG676-5C v3 3.3V only (4) Spartan-3E XC3S1200E-FG400-5C v3 3.3V only PCI64/33 Kintex-7 XC7K70T-SBG324-1C/I v4 3.3V only Kintex-7 XC7K70T-FBG484-1C/I v4 3.3V only Kintex-7 XC7K70T-FBG676-1C/I v4 3.3V only Kintex-7 XC7K160T-FBG484-1C/I v4 3.3V only Kintex-7 XC7K160T-FBG676-1C/I v4 3.3V only Kintex-7 XC7K160T-FFG676-1C/I v4 3.3V only Kintex-7 XC7K325T-FBG676-1C/I v4 3.3V only Kintex-7 XC7K325T-FBG900-1C/I v4 3.3V only Kintex-7 XC7K325T-FFG676-1C/I v4 3.3V only Kintex-7 XC7K325T-FFG900-1C/I v4 3.3V only Kintex-7 XC7K355T-FFG901-1C/I v4 3.3V only Kintex-7 XC7K410T-FBG676-1C/I v4 3.3V only Kintex-7 XC7K410T-FBG900-1C/I v4 3.3V only DS205 October 16, 2012 www.xilinx.com 2 Product Specification v3.167 & v4.18