L1206MR100FBT Vishay

333 3 L www.vishay.com Vishay Sfernice SMD Wraparound Ultra Low Value Thin Film Resistors FEATURES NiCr + Ta O resistive layer 2 5 Pre-soldered or gold terminations No inductance for high frequency applications Available Alumina substrates for high power handling capability Available Resistance range: 0.1 to 9.99 Available TCR down to 50 ppm/C Power rating: up to 2 W at +70 C Withstand AEC-Q200 humidity test ADDITIONAL RESOURCES Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 3D Models Note * This datasheet provides information about parts that are With extremely low resistance and high power capabilities, RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. these ultra low value resistors are available with solderable Please see the information / tables in this datasheet for details or weldable terminations. STANDARD ELECTRICAL SPECIFICATIONS RATED POWER LIMITING ELEMENT TEMPERATURE RESISTANCE RANGE TOLERANCE MODEL SIZE P VOLTAGE COEFFICIENT 70 C % W V ppm/C L0603 0603 0.1 to 9.99 0.125 50 1, 2, 3, 5, 10 50, 100, 200, 300 L0805 0805 0.1 to 9.99 0.2 50 1, 2, 3, 5, 10 50, 100, 200, 300 L1206 1206 0.1 to 9.99 0.33 50 1, 2, 3, 5, 10 50, 100, 200, 300 L1505 1505 0.1 to 9.99 0.5 50 1, 2, 3, 5, 10 50, 100, 200, 300 L2010 2010 0.1 to 9.99 1.0 50 1, 2, 3, 5, 10 50, 100, 200, 300 (1) L2512 2512 0.1 to 9.99 2.0 50 1, 2, 3, 5, 10 50, 100, 200, 300 Note (1) With special assembly care CLIMATIC SPECIFICATIONS TOLERANCE AND TCR VS. OHMIC VALUE TIGHTEST BEST Operating temperature OHMIC VALUE -55 C +155 C TOLERANCE TCR TERMINATIONS range RANGE in (%) (ppm/C) 0R1 < 0R25 1 300 N or B MECHANICAL SPECIFICATIONS 0R25 < 0R5 1 200 N or B Substrate Alumina 0R5 < 2R5 1 100 N or B Technology NiCr + Ta O 2 5 2R5 < 9R99 1 50 N or B Coating Silicone 0R1 < 0R25 5 300 G Solderable 0R25 < 0R5 5 200 G B type: SnPb over nickel barrier Terminations N type: SnAg over nickel barrier 0R < 1R 5 100 G G type: Gold over nickel barrier 1R < 2R5 3 100 G Note 2R5 to 9R99 3 50 G Refer to Application Note Guidelines for Vishay Sfernic e Resistive and Inductive Components (document number: 52029) for recommended reflow profile. Profile 3 applies Revision: 31-Jan-2020 Document Number: 53018 1 For technical questions, contact: sferthinfilm vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 DDD DL www.vishay.com Vishay Sfernice DIMENSIONS in millimeters (inches) A B C D E AB C D/E CASE SIZE 0.152 ( 0.006) 0.127 ( 0.005) 0.127 (+ 0.005) 0.127 ( 0.005) 0603 1.52 (0.060) 0.85 (0.033) 0.38 (0.015) 0805 1.91 (0.075) 1.27 (0.050) 1206 3.06 (0.120) 1.60 (0.063) 0.40 (0.016) 0.5 (0.020) 1505 3.81 (0.150) 1.32 (0.052) 2010 5.08 (0.200) 2.54 (0.100) 0.48 (0.019) 2512 6.30 (0.248) 3.30 (0.129) SUGGESTED LAND PATTERN in millimeters (inches) (to IPC-7351A) G min. X max. Z max. CASE SIZE Z G X max. min. max. 0603 2.37 (0.093) 0.35 (0.014) 0.98 (0.039) 0805 2.76 (0.109) 0.74 (0.029) 1.40 (0.055) 1206 3.91 (0.154) 1.85 (0.073) 1.73 (0.068) 1505 4.66 (0.183) 2.44 (0.096) 1.45 (0.057) 2010 5.93 (0.233) 3.71 (0.146) 2.67 (0.105) 2512 7.15 (0.281) 4.93 (0.194) 3.43 (0.135) Option: Enlarged Terminations: 0063 For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heat sinks (see application note: Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA Arrays, CHP Thick Film): www.vishay.com/doc 53048). For enlarged terminations: Please consult Vishay Sfernice. Revision: 31-Jan-2020 Document Number: 53018 2 For technical questions, contact: sferthinfilm vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000