74VHC86FT Toshiba

74VHC86FT CMOS Digital Integrated Circuits Silicon Monolithic 74VHC86FT74VHC86FT74VHC86FT74VHC86FT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Quad Exclusive OR Gate 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHC86FT is an advanced high speed CMOS QUAD EXCLUSIVE OR GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is includes on output buffer, which provide high noise immunity and stable output. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: t = 4.8 ns (typ.) at V = 5.0 V pd CC (4) Low power dissipation: I = 2.0 A (max) at T = 25 CC a (5) High noise immunity: V = V = 28 % V (min) NIH NIL CC (6) Power down protection is provided on all inputs. (7) Balanced propagation delays: t t PLH PHL (8) Wide operating voltage range: V = 2.0 V to 5.5 V CC(opr) (9) Low noise: V = 0.8 V (max) OLP (10) Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 86 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP14B Start of commercial production 2013-05 2017 Toshiba Corporation 2017-02-22 1 Rev.4.074VHC86FT 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. 7. 7. IEC Logic SymbolIEC Logic SymbolIEC Logic SymbolIEC Logic Symbol 2017 Toshiba Corporation 2017-02-22 2 Rev.4.0