STM32F437xx STM32F439xx ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera&LCD-TFT Datasheet - production data Features Core: ARM 32-bit Cortex -M4 CPU with FPU, LQFP100 (14 14 mm) Adaptive real-time accelerator (ART LQFP144 (20 20 mm) UFBGA169 (7 7 mm) Accelerator) allowing 0-wait state execution WLCSP143 LQFP176 (24 24 mm) UFBGA176 (10 x 10 mm) from Flash memory, frequency up to 180 MHz, LQFP208 (28 x 28 mm) TFBGA216 (13 x 13 mm) MPU, 225 DMIPS/1.25 DMIPS/MHz Up to 168 I/O ports with interrupt capability (Dhrystone 2.1), and DSP instructions Up to 164 fast I/Os up to 90 MHz Memories Up to 166 5 V-tolerant I/Os Up to 2 MB of Flash memory organized into Up to 21 communication interfaces two banks allowing read-while-write 2 Up to 3 I C interfaces (SMBus/PMBus) Up to 256+4 KB of SRAM including 64-KB Up to 4 USARTs/4 UARTs (11.25 Mbit/s, of CCM (core coupled memory) data RAM ISO7816 interface, LIN, IrDA, modem Flexible external memory controller with up control) to 32-bit data bus: SRAM,PSRAM,SDRAM/LPSDR SDRAM , Up to 6 SPIs (45 Mbits/s), 2 with muxed 2 full-duplex I S for audio class accuracy via Compact Flash/NOR/NAND memories internal audio PLL or external clock LCD parallel interface, 8080/6800 modes 1 x SAI (serial audio interface) LCD-TFT controller up to XGA resolution with 2 CAN (2.0B Active) and SDIO interface dedicated Chrom-ART Accelerator for Advanced connectivity enhanced graphic content creation (DMA2D) USB 2.0 full-speed device/host/OTG Clock, reset and supply management controller with on-chip PHY 1.7 V to 3.6 V application supply and I/Os USB 2.0 high-speed/full-speed POR, PDR, PVD and BOR device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI 4-to-26 MHz crystal oscillator 10/100 Ethernet MAC with dedicated DMA: Internal 16 MHz factory-trimmed RC (1% supports IEEE 1588v2 hardware, MII/RMII accuracy) 8- to 14-bit parallel camera interface up to 32 kHz oscillator for RTC with calibration 54 Mbytes/s Internal 32 kHz RC with calibration Low power Cryptographic acceleration: hardware acceleration for AES 128, 192, 256, Triple Sleep, Stop and Standby modes DES, HASH (MD5, SHA-1, SHA-2), and HMAC V supply for RTC, 2032 bit backup BAT registers + optional 4 KB backup SRAM True random number generator 312-bit, 2.4 MSPS ADC: up to 24 channels CRC calculation unit and 7.2 MSPS in triple interleaved mode RTC: subsecond accuracy, hardware calendar 212-bit D/A converters 96-bit unique ID General-purpose DMA: 16-stream DMA Table 1. Device summary controller with FIFOs and burst support Reference Part number Up to 17 timers: up to twelve 16-bit and two 32- STM32F437VG, STM32F437ZG, STM32F437IG, bit timers up to 180 MHz, each with up to 4 STM32F437xx STM32F437VI, STM32F437ZI, STM32F437II, IC/OC/PWM or pulse counter and quadrature STM32F437AI (incremental) encoder input STM32F439VI, STM32F439VG, STM32F439ZG, Debug mode STM32F439ZI, STM32F439IG, STM32F439II, STM32F439xx STM32F439BG, STM32F439BI, STM32F439NI, SWD & JTAG interfaces STM32F439AI, STM32F439NG Cortex-M4 Trace Macrocell January 2016 DocID024244 Rev 9 1/233 This is information on a product in full production. www.st.comContents STM32F437xx and STM32F439xx Contents 1 Introduction . 12 2 Description 13 2.1 Full compatibility throughout the family 16 3 Functional overview 19 3.1 ARM Cortex-M4 with FPU and embedded Flash and SRAM . 19 3.2 Adaptive real-time memory accelerator (ART Accelerator) . 19 3.3 Memory protection unit . 19 3.4 Embedded Flash memory 20 3.5 CRC (cyclic redundancy check) calculation unit . 20 3.6 Embedded SRAM . 20 3.7 Multi-AHB bus matrix 20 3.8 DMA controller (DMA) . 21 3.9 Flexible memory controller (FMC) 22 3.10 LCD-TFT controller (available only on STM32F439xx) 22 3.11 Chrom-ART Accelerator (DMA2D) 23 3.12 Nested vectored interrupt controller (NVIC) . 23 3.13 External interrupt/event controller (EXTI) . 23 3.14 Clocks and startup 23 3.15 Boot modes . 24 3.16 Power supply schemes 24 3.17 Power supply supervisor . 24 3.17.1 Internal reset ON 24 3.17.2 Internal reset OFF . 25 3.18 Voltage regulator . 26 3.18.1 Regulator ON . 26 3.18.2 Regulator OFF 27 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability 30 3.19 Real-time clock (RTC), backup SRAM and backup registers 30 3.20 Low-power modes 31 3.21 V operation . 32 BAT 2/233 DocID024244 Rev 9