STEVAL-PCC010V2

ST802RT1A ST802RT1B 10/100 real-time Ethernet 3.3 V transceiver Features IEEE802.3 10Base-T and IEEE802.3u 100Base-TX, 100Base-FX (ST802RT1B only) transceiver Support for IEEE802.3x flow control Provides full-duplex operation in both 100 Mbps and 10 Mbps modes LQFP48 Register bit strap during HW reset Auto MDI-X for 10/100 Mb/s Auto-negotiation Building automation Provides loop-back mode for diagnostics Telecom infrastructure Programmable LED display for operating mode and functionality signaling Description MII / RMII interface The ST802RT1x is a high-performance fast MDC / MDIO serial management interface Ethernet physical layer interface for 10Base-T, Optimized deterministic latency for real-time 100Base-TX and 100Base-FX applications. It is Ethernet operation designed using advanced CMOS technology to provide MII and RMII interfaces for easy Supports external transformer with turn ratio attachment to 10/100 media access controllers 1.414:1 on Tx/Rx side (MAC). The ST802RT1x supports the 100Base- Self-termination transceiver for external TX of IEEE802.3u and 10Base-T of IEEE802.3i components and power saving and 100Base FX of IEEE 802.3u (B version only). Operation from single 3.3 V supply The ST802RT1x supports both half-duplex and full-duplex operation at 10 and 100 Mbps High ESD tolerance operation. Its operating mode can be set using 48-pin LQFP 7 x 7 package auto-negotiation, parallel detection or manual Extended temp. range: -40 C to +105 C control. It allows for the support of auto- negotiation functions for speed and duplex Power dissipation < 315 mW (typ) detection. The automatic MDI / MDIX feature compensates for the use of a crossover cable. Applications With auto MDIX, the ST802RT1x automatically detects what is on the other end of the network Industrial control cable and switches the TX & RX pin functionality Factory automation accordingly. High-end peripherals Table 1. Device summary Order codes Temperature range Package ST802RT1AFR - 40 to 105 C LQFP48 ST802RT1BFR - 40 to 105 C LQFP48 February 2010 Doc ID 17049 Rev 1 1/58 www.st.com 58Contents ST802RT1A, ST802RT1B Contents 1 Features . 6 1.1 Physical layer . 6 1.2 LED display 6 1.3 Package . 6 2 Device block diagram 7 3 System and block diagrams . 8 4 Pin configuration 9 5 Pin description 11 6 Registers and descriptors description . 17 6.1 Register list 17 6.2 Register description . 18 7 Device operation . 38 7.1 100Base-TX transmit operation 38 7.2 100Base-TX receive operation . 39 7.3 10Base-T transmit operation 40 7.4 10Base-T receive operation . 40 7.5 Loop-back operation . 40 7.6 Full-duplex and half-duplex operation . 40 7.7 Auto-negotiation operation 40 7.8 Power-down / interrupt . 41 7.9 Power-down operation . 41 7.10 Interrupt mechanisms 41 7.11 LED display operation . 42 7.12 Reset operation 43 7.13 Preamble suppression . 43 7.14 Remote fault . 43 7.15 Transmit isolation . 44 2/58 Doc ID 17049 Rev 1