PSD835G2-90U

PSD835G2 Flash PSD, 5 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM Features Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank flash memories 4 Mbits of primary Flash memory (8 uniform sectors, 64 Kbytes) 256 Kbits of secondary Flash memory with 4 sectors LQFP80 (U) Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of SRAM Page register 52 reconfigurable I/O ports Internal page register that can be used to Enhanced JTAG serial port expand the microcontroller address space PLD with macrocells by a factor of 256 Over 3000 gates of PLD: CPLD and DPLD Programmable power management CPLD with 16 output macrocells (OMCs) High endurance and 24 Rev 5 macrocells (IMCs) 100,000 Erase/WRITE cycles of Flash DPLD - user defined internal chip select memory decoding 1,000 Erase/Write cycles of PLD 52 individually configurable I/O port pins 15 year data retention They can be used for the following functions: 5 V10% single supply voltage MCU I/Os Standby current as low as 50 A PLD I/Os Memory speed Latched MCU address output 70 ns Flash memory and SRAM access Special function I/Os. time for V = 4.5 to 5.5 V I/O ports may be configured as open-drain CC 90 ns Flash memory and SRAM access outputs. time for V = 4.5 to 5.5 V CC In-system programming (ISP) with JTAG ECOPACK package Built-in JTAG compliant serial port allows full-chip in-system programmability Efficient manufacturing allow easy product testing and programming Use low cost FlashLINK cable with PC February 2009 Rev 5 1/120 www.st.com 1 Obsolete Product(s) - Obsolete Product(s)Contents PSD835G2 Contents 1 Description 11 1.1 In-System Programming (ISP) via JTAG . 11 1.1.1 First time programming . 11 1.1.2 Inventory build-up of preprogrammed devices 11 1.1.3 Expensive sockets . 11 1.2 In-application programming (IAP) . 12 1.2.1 Simultaneous READ and WRITE to Flash memory 12 1.2.2 Complex memory mapping 12 1.2.3 Separate program and data space 12 1.3 PSDsoft . 12 2 PSD architectural overview 19 2.1 Memory 19 2.2 Page register 19 2.3 PLDs 19 2.4 I/O ports 20 2.5 MCU bus interface 20 2.6 JTAG port . 20 2.7 In-system programming (ISP) . 20 2.8 In-application reprogramming (IAP) . 21 2.9 Power management unit (PMU) 21 3 Development system . 22 4 PSD register description and address offset 24 5 Register bit definition . 26 6 Detailed operation 32 6.1 Memory blocks . 32 6.2 Primary Flash memory and secondary Flash memory description . 33 6.3 Memory Block Select signals 33 6.4 Upper and lower block in main Flash sector . 33 2/120 Obsolete Product(s) - Obsolete Product(s)