M34E02-FDW1TP

M34E02-F 2-Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1, DDR2 and DDR3) DRAM modules Datasheet - production data Features 2-Kbit EEPROM for DDR1, DDR2 and DDR3 serial presence detect Backward compatible with the M34C02 Permanent and reversible software data protection for lower 128 bytes UFDFPN8 (MC) 2 100 kHz and 400 kHz I C bus serial interface 2 x 3 mm Single supply voltage: 1.7 V to 5.5 V Byte and Page Write (up to 16 bytes) Self-timed write cycle Noise filtering Schmitt trigger on bus inputs TSSOP8 (DW) Noise filter on bus inputs 4.4 3 mm Enhanced ESD/latch-up protection More than 1 million erase/write cycles More than 40 years data retention ECOPACK (RoHS compliant) packages Packages: ECOPACK2 (RoHS-compliant and Halogen-free) May 2013 DocID10367 Rev 14 1/36 This is information on a product in full production. www.st.com 1Contents M34E02-F Contents 1 Description . 6 2 Signal description . 8 2.1 Serial Clock (SCL) . 8 2.2 Serial Data (SDA) 8 2.3 Chip Enable (E0, E1, E2) 8 2.4 Write Control (WC) . 9 2.5 Supply voltage (V ) . 9 CC 2.5.1 Operating supply voltage (V ) 9 CC 2.5.2 Power-up conditions 9 2.5.3 Device reset . 9 2.5.4 Power-down conditions . 10 3 Device operation . 12 3.1 Start condition 12 3.2 Stop condition 12 3.3 Acknowledge bit (ACK) 12 3.4 Data input . 12 3.5 Memory addressing . 13 3.6 Setting the write-protection 14 3.6.1 SWP and CWP . 14 3.6.2 PSWP 14 3.7 Write operations 15 3.7.1 Byte Write . 15 3.7.2 Page Write . 15 3.7.3 Minimizing system delays by polling on ACK 17 3.8 Read operations 17 3.8.1 Random Address Read . 17 3.8.2 Current Address Read 17 3.8.3 Sequential Read 17 3.8.4 Acknowledge in Read mode . 18 4 Initial delivery state . 19 2/36 DocID10367 Rev 14