Si5326 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features Generates any frequency from 2 kHz Dual clock outputs with selectable to 945 MHz and select frequencies to signal format 1.4 GHz from an input frequency of Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 2 kHz to 710 MHz Ultra-low jitter clock outputs with jitter 255/236) generation as low as 0.3 ps rms LOL, LOS, FOS alarm outputs Digitally-controlled output phase (50 kHz80 MHz) Integrated loop filter with selectable adjustment 2 loop bandwidth (60 Hz to 8.4 kHz) I C or SPI programmable Ordering Information: Meets OC-192 GR-253-CORE jitter On-chip voltage regulator for specifications See page 65. 1.8 5%, 2.5 10%, or 3.3 V 10% Dual clock inputs with manual or operation automatically controlled hitless Small size: 6 x 6 mm 36-lead QFN switching (LVPECL, LVDS, CML, Pb-free, ROHS compliant Pin Assignments CMOS) Applications SONET/SDH OC-48/OC-192/STM- Optical modules 36 35 34 33 32 31 30 29 28 16/STM-64 line cards Wireless basestations RST 1 27 SDI NC 2 26 A2 SS ITU G.709 and custom FEC line Data converter clocking INT C1B 3 25 A1 cards xDSL C2B 4 24 A0 GbE/10GbE, 1/2/4/8/10G Fibre PDH clock synthesis GND VDD 5 23 SDA SDO Pad XA 6 22 SCL Channel line cards Test and measurement XB 7 21 CS CA GbE/10GbE Synchronous Ethernet Broadcast video GND 8 20 INC DEC NC 9 19 10 11 12 13 14 15 16 17 18 Description The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1ps jitter performance. The Si5326 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The Si5326 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through 2 an I C or SPI interface. The Si5326 is based on Skyworks Solutions 3rd-generation DSPLL technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice October 29, 2021 VDD CMODE RATE0 CKOUT2+ CKIN2+ CKOUT2 CKIN2 NC NC VDD RATE1 GND CKIN1+ NC CKIN1 CKOUT1 LOL CKOUT1+Si5326 Functional Block Diagram Xtal or Refclock Hitless Switching N31 CKIN1 Mux N1 LS CKOUT1 CKIN2 N32 DSPLL N1 HS CKOUT2 N2 LS Xtal/Refclock N2 Loss of Signal/ VDD (1.8, 2.5, or 3.3 V) Frequency Offset Signal Detect Control GND Loss of Lock 2 Clock Select I C/SPI Port Device Interrupt Skew Control Rate Select 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice October 29, 2021