Si510/511 CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ Features Si5602 Supports any frequency from 3.3, 2.5, or 1.8 V operation 100 kHz to 250 MHz Differential (LVPECL, LVDS, Low jitter operation HCSL) or CMOS output options 2 to 4 week lead times Optional integrated 1:2 CMOS fanout buffer Total stability includes 10-year aging Runt suppression on OE and power on Comprehensive production test coverage includes crystal ESR and Industry standard 5 x 7 and DLD 3.2x 5 mm packages On-chip LDO regulator for power Pb-free, RoHS compliant supply noise filtering o 40 to 85 C operation Ordering Information: Applications See page 14. SONET/SDH/OTN 3G-SDI/HD-SDI/SDI Gigabit Ethernet Telecom Pin Assignments: Fibre Channel/SAS/SATA Switches/routers See page 12. PCI Express FPGA/ASIC clock generation Description The Si510/511 XO utilizes Silicon Laboratories advanced DSPLL technology V 1 4 DD OE to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si510/511 uses one fixed crystal and Silicon Labs proprietary DSPLL synthesizer to generate any frequency across this range. This IC-based approach allows GND 2 3 CLK the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. In addition, this solution provides superior Si510 (CMOS) supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si510/511 is factory- V NC 1 6 DD configurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. Specific OE 2 5 CLK configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom GND 3 4 CLK+ frequency oscillators. Functional Block Diagram Si510(LVDS/LVPECL/HCSL/ Dual CMOS) V DD 1 6 VV OEOE 1 6 DDDD OE Low Noise Regulator Fixed Any-Frequency CLK+ NC 2 5 NC 2 5 CLCLKK Frequency 0.1 to 250 MHz Oscillator DSPLL Synthesis CLK GND 3 4 GND 3 4 CLCLK+K+ Si511(LVDS/LVPECL/HCSL/ GND Dual CMOS) Rev. 1.1 1/13 Copyright 2013 by Silicon Laboratories Si510/511Si510/511 2 Rev. 1.1