19-Output DB1900Z Low-Power Derivative 9ZXL1950 with 85ohm Terminations DATASHEET General Description Features/Benefits The 9ZXL1950 is a DB1900Z derivative buffer utilizing LP-HCSL outputs up to 90% IO power reduction, better Low-Power HCSL (LP-HCSL) outputs to increase edge rates signal integrity over long traces on long traces, reduce board space, and reduce power Direct connect to 85 transmission lines eliminates 76 2 consumption more than 50% from the original 9ZX21901.It is termination resistors, saves 130mm area pin-compatible to the 9ZXL1930 and fully integrates the Pin compatible to the 9ZXL1930 easy upgrade to reduced output terminations. It is suitable for PCI-Express Gen1/2/3 or board space QPI/UPI applications, and uses a fixed external feedback to 72-pin VFQFPN package smallest 19-output Z-buffer maintain low drift for demanding QPI/UPI applications. Fixed feedback path ~0ps input-to-output delay Recommended Application 9 Selectable SMBus addresses multiple devices can share same SMBus segment Buffer for Romley, Grantley and Purley Servers Separate VDDIO for outputs allows maximum power Output Features savings PLL or bypass mode PLL can dejitter incoming clock 19 LP-HCSL output pairs w/integrated terminations (Zo = 85 100MHz & 133.33MHz PLL mode legacy QPI support Selectable PLL BW minimizes jitter peaking in downstream Key Specifications PLL s Cycle-to-cycle jitter: <50ps Spread spectrum compatible tracks spreading input clock Output-to-output skew: <50ps for EMI reduction Input-to-output delay variation: <50ps SMBus Interface unused outputs can be disabled Phase jitter: PCIe Gen3 <1ps rms Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms Block Diagram FBOUT NC Z-PLL (SS Compatible) DIF IN DIF(18:0) DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD Logic SMB A0 tri SMB A1 tri SMBDAT SMBCLK 9ZXL1950 MAY 11, 2017 1 2017 Integrated Device Technology, Inc.DIF6 DIF6 GND VDDIO DIF5 DIF5 DIF4 DIF4 VDD GND DIF3 DIF3 DIF2 DIF2 GND VDDIO DIF1 DIF1 9ZXL1950 DATASHEET Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DIF12 VDDA 1 54 DIF12 GNDA 2 53 VDDIO 100M 133M 3 52 GND vHIBW BYPM LOBW 4 51 DIF11 CKPWRGD PD 5 50 DIF11 GND 6 49 DIF10 VDDR 7 48 DIF10 DIF IN 8 47 9ZXL1950 GND DIF IN 9 46 (epad should be connected to GND and is VDD SADR0 tri 10 45 pin 73) DIF9 SMBDAT 11 44 DIF9 SMBCLK 12 43 DIF8 SADR1 tri 13 42 DIF8 FBOUT NC 14 41 VDDIO FBOUT NC 15 40 GND GND 16 39 DIF7 DIF0 17 38 N/A 1530 DIF7 DIF0 18 37 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Note: Pins with prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm Pins with v prefix have internal 120K pullup/pulldown (biased to VDD/2) Power Management Table Inputs Outputs Control Bits PLL State DIF IN/ SMBus DIFx/ FBOUT NC/ CKPWRGD PD DIF IN EN bit DIFx FB OUT NC 0 X X Low/Low Low/Low OFF 0 Low/Low Running ON 1 Running 1 Running Running ON Power Connections PLL Operating Mode Pin Number HiBW BypM LoBW Byte0, bit (7:6) Description VDD VDDIO GND Low ( PLL Low BW) 00 1 2 Analog PLL Mid (Bypass) 01 76Analog Input High (PLL High BW) 11 16, 22, 27, 34, NOTE: PLL is off in Bypass mode 21, 33, 40, 28, 45, 64 39, 46, 51, 58, DIF clocks 52, 57, 69 63, 70, 73 Tri-level Input Thresholds Level Voltage Functionality at Power-up (PLL mode) Low <0.8V DIF IN DIFx Mid 1.2<Vin<1.8V 100M 133M (MHz) (MHz) High Vin > 2.2V 1 100.00 DIF IN 0 133.33 DIF IN 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE WITH 85OHM TERMINATIONS2 MAY 11, 2017 DIF18 DIF18 GND VDDIO DIF17 DIF17 DIF16 DIF16 VDD GND DIF15 DIF15 DIF14 DIF14 GND VDDIO DIF13 DIF13