DATASHEET Fifteen Output Differential Buffer w/2 input mux for PCIe 9EX21531 Gen1/2/3 Recommended Application: Features/Benefits: 15 Output PCIe G3 Differential Buffer with 2:1 input mux Pin compatible to 9EX21501/ Easy PCIe Gen3 upgrade 4 Selectable SMBus Addresses/Mulitple devices can General Description share the same SMBus Segment The ICS9EX21531 provides 15 output clocks for PCIe Gen1/ 8 dedicated and 2 group OE pins/Hardware control of 2/3 applications. The 9EX21531 has 4 selectable SMBus the outputs addresses, and dedicated CKPWRGD/PD and VDDA pins for easy board design. A differential clock from a CK410B+ PLL or bypass mode/PLL can dejitter incoming clock or CK420BQ main clock generator, such as the ICS932S421, Selectable PLL bandwidth/minimizes jitter peaking in drives the ICS9EX21531. In fanout mode, the 9EX21531 downstream PLL s provides outputs up to 166MHz. Spread Spectrum Compatible/tracks spreading input clock for low EMI Output Features: SMBus Interface/unused outputs can be disabled 15 - 0.7V current mode differential HSCL output pairs Undriven differential outputs in Power Down mode/ Easy power management Key Specifications: Cycle-to-cycle jitter <50ps Output-to-output skew < 150 ps PCIe Gen3 phase jitter < 1.0ps RMS Functional Block Diagram OE(13:14) 10 OE(5:12) , OE 01234 CLKA IN PLL CLKA IN (SS Compatible) 15 DIF(14:0) CLKB IN CLKB IN HIBW BYPM LOBW CKPWRGD/PD SMB A0 Logic SMB A1 SEL A B SMBDAT SMBCLK IREF IDT Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 1679C10/25/16 1DIF 0 DIF 0 OE 01234 VDD CLKB IN CLKB IN GND CLKA IN CLKA IN VDDA GNDA IREF DIF 14 DIF 14 OE13 14 VDD 9EX21531 Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 OE9 1 48 DIF 6 DIF 9 2 47 DIF 6 DIF 9 3 46 OE6 OE10 4 45 DIF 5 DIF 10 5 44 DIF 5 DIF 10 6 43 OE5 OE11 7 42 DIF 4 DIF 11 8 41 DIF 4 9EX21531 DIF 11 9 40 DIF 3 GND 10 39 DIF 3 VDD 11 38 GND DIF 12 12 37 VDD DIF 12 13 36 DIF 2 OE12 14 35 DIF 2 DIF 13 15 34 DIF 1 DIF 13 16 33 DIF 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Power Groups HIBW BYPM LOBW Selection (Pin 54) Pin Number Description State Voltage Mode VDD GND Low <0.8V Low BW 23 22 Main PLL, Analog Mid 1.2<Vin<1.8V Bypass 29 26 Input buffers High Vin > 2.0V High BW 11,17,37,49,53,64 10, 38 DIF clocks SMBus Address Selection (pins 57, 58) Power Down Functionality SMB A1 SMB A0 Address INPUTS OUTPUTS 00 D4 PLL State CKPWRGD/PD Input DIF x 01 D6 1 Running Running ON 10 D8 0X Hi-Z OFF 11 DA IDT Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 1679C10/25/16 2 VDD OE8 DIF 8 DIF 8 CKPWRGD/PD SEL A B SMB A0 SMB A1 SMBDAT SMBCLK HIBW BYPM LOBW VDD DIF 7 DIF 7 OE7 VDD