Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V 8535-21 LVPECL CLock Generator Datasheet General Description Features The 8535-21 is a low skew, high performance 1-to-2 Two differential 3.3V LVPECL outputs LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The 8535-21 has Selectable CLK0 or CLK1 inputs for redundant and multiple two single-ended clock inputs. The single-ended clock input accepts frequency fanout applications LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL CLK0 or CLK1 can accept the following input levels: levels. The clock enable is internally synchronized to eliminate runt LVCMOS or LVTTL clock pulses on the output during asynchronous Maximum output frequency: 266MHz assertion/deassertion of the clock enable pin. Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels Guaranteed output and part-to-part skew characteristics make the Output skew: 20ps (maximum) 8535-21 ideal for those applications demanding well defined Part-to-part skew: 300ps (maximum) performance and repeatability. Propagation delay: 1.6ns (maximum) Additive phase jitter, RMS: 0.03ps (typical) 3.3V operating supply 0C to 70C ambient operating temperature Industrial temperature information available upon request Available in lead-free (RoHS 6) Block Diagram Pin Assignment Pullup CLK EN V 1 14 V EE CC D Q CLK EN 2 13 Q0 Q0 LE CLK SEL 3 12 Pulludown CLK0 0 CLK0 4 11 nc Q0 V EE 5 10 Q1 Pulludown Q0 CLK1 6 9 Q1 CLK1 1 V V CC 7 8 CC Q1 Pulludown CLK SEL Q1 8535-21 14 Lead TSSOP 4.40mm x 5.0mm x 0.925mm package body G Package Top View 2015 Integrated Device Technology, Inc. 1 Revision B, December 8, 20158535-21 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 5 V Power Negative supply pins. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Input Pullup When LOW, Qx outputs are forced low, Qx outputs are forced high. LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. 3 CLK SEL Input Pulldown When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels. 4, 6 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 7, 8, 14 V Power Power supply pins. CC 9, 10 Q1, Q1 Output Differential output pair. LVPECL interface levels. 11 nc Unused No connect. 12, 13 Q0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2015 Integrated Device Technology, Inc. 2 Revision B, December 8, 2015