FemtoClock Crystal-to-LVDS/LVCMOS 8402015 Frequency DATA SHEET General Description Features 8402015 is a low phase noise Clock Synthesizer and is a member of Three banks of outputs: the high performance clock solutions from IDT. The device provides Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz three banks of outputs and a reference clock. Each bank can be or 50MHz enabled by using output enable pins. A 25MHz or 50MHz, 18pF Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz parallel resonant crystal is used to generate 25MHz LVCMOS, 125MHz LVCMOS and 125MHz LVDS outputs. 8402015 is Bank C: three differential LVDS outputs at 125MHz packaged in a small, 32-pin VFQFN package that is optimum for Reference LVCMOS/LVTTL output at 25MHz applications with space limitations. Crystal input frequency: 25MHz Maximum output frequency: 125MHz RMS phase jitter 125MHz, using a 25MHz crystal (637kHz - 62.5MHz): 0.373ps (typical) LVDS output RMS phase jitter 25MHz, using a 25MHz crystal (12kHz - 1MHz): 0.64ps (typical) LVCMOS output Full 3.3V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment 32 31 30 29 28 27 26 25 VDDO REF 1 VDDO C 24 REF OUT 2 23 nQC2 GND 3 QC2 22 GND 4 nC1 21 QA0 QC1 5 20 QA1 6 nQC0 19 QA2 7 QC0 18 VDDO A 8 17 VDDO C 9 10 11 12 13 14 15 16 8402015 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 8402015 Rev B 7/2/15 1 2015 Integrated Device Technology, Inc. VDDO B GND QB0 XTAL OUT QB1 XTAL IN QB2 OE2 GND OE1 MR OE0 VDD VDDA GND GND8402015 DATA SHEET Block Diagram OE1 = Pullup OE 3 OE0, OE2 = Pulldown OE 2:0 OE 2:0 LVCMOS - 25MHz or LOGIC 50MHz QA0 10 QA1 20 QA2 25MHz XTAL IN LVCMOS - 125MHz OSC QB0 VCO Phase XTAL OUT 500MHz Detector QB1 4 QB2 20 LVDS - 125MHz QC0 nQC0 QC1 4 nQC1 QC2 nQC2 Pulldown MR LVCMOS - 25MHz REF OUT FEMTOCLOCK CRYSTAL-TO-LVDS/LVCMOS FREQUENCY 2 Rev B 7/2/15