DATA SHEET www.onsemi.com High Speed Half-Bridge Driver for GaN Power Switches QFN15 4x4, 0.5P CASE 485FN NCP51820 MARKING DIAGRAM The NCP51820 highspeed, gate driver is designed to meet the stringent requirements of driving enhancement mode (emode), high 51820A electron mobility transistor (HEMT) and gate injection transistor ALYW (GIT), gallium nitrade (GaN) power switches in offline, halfbridge power topologies. The NCP51820 offers short and matched propagation delays with advanced level shift technology providing 51820A = Specific Device Code 3.5 V to +650 V (typical) common mode voltage range for the A = Assembly Site L = Wafer Lot Number highside drive and 3.5 V to +3.5 V common mode voltage range for YW = Assembly Start Week the lowside drive. In addition, the device provides stable dV/dt = PbFree Package operation rated up to 200 V/ns for both driver output stages in high (Note: Microdot may be in either location) speed switching applications. To fully protect the gate of the GaN power transistor against PIN ASSIGNMENT excessive voltage stress, both drive stages employ a dedicated voltage regulator to accurately maintain the gate source drive signal amplitude. The circuit actively regulates the drivers bias rails and thus protects against potential gatesource overvoltage under various operating conditions. VDDH 1 13 EN The NCP51820 offers important protection functions such as independent undervoltage lockout (UVLO), monitoring VDD bias HOSRC 2 12 HIN voltage and VDDH and VDDL driver bias and thermal shutdown NCP51820 HOSNK 3 11 LIN based on die junction temperature of the device. Programmable (Top View) deadtime control can be configured to prevent crossconduction. SW 4 10 SGND 9 DT Features 650 V, Integrated HighSide and LowSide Gate Drivers UVLO Protections for VDD High and LowSide Drivers Dual TTL Compatible Schmitt Trigger Inputs Split Output Allows Independent TurnON/TurnOFF Adjustment Source Capability: 1 A Sink Capability: 2 A ORDERING INFORMATION Separated HO and LO Driver Output Stages 1 ns Rise and Fall Times Optimized for GaN Devices Device Package Shipping SW and PGND: Negative Voltage Transient up to 3.5 V NCP51820AMNTWG QFN15 4000 / Tape (PbFree) & Reel 200 V/ns dV/dt Rating for all SW and PGND Referenced Circuitry For information on tape and reel specifications, Maximum Propagation Delay of Less Than 50 ns including part orientation and tape sizes, please Matched Propagation Delays to Less Than 5 ns refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. User Programmable DeadTime Control Thermal Shutdown (TSD) Typical Applications Driving GaN Power Transistors used in Full or HalfBridge, LLC, Active Clamp Flyback or Forward, Totem Pole PFC and Synchronous Rectifier Topologies Industrial Inverters and Motor Drives AC to DC Converters Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: August, 2021 Rev. 5 NCP51820/D 15 VBST VDDL 5 LOSRC 6 LOSNK 7 PGND 8 14 VDDDRIVER DRIVER NCP51820 VIN VDD VDDH EN 1 13 PWM HOSRC HIN C 2 12 or HOSNK LIN NCP51820 DSP 3 11 (Top View) SW SGND 4 10 POWER DT STAGE 9 Figure 1. Typical Application Schematic VDDH VBST VDDH REGULATOR VDDH HOSRC UVLO VDD S HO Q HOSNK LEVEL SHIFTER VDD R UVLO 8.5V/8V (ON/OFF) SW EN SCHMITT TRIGGER INPUT VDDL HIN VDDL SHOOT THOUGH REGULATOR PREVENTION LIN CYCLEBy VDDL LOSRC CYCLE EDGE UVLO DT TRIGGERED SHUTDOWN LO DELAY LOSNK DEADTIME LEVEL SHIFTER MODE CONTROL SGND PGND Figure 2. Internal Block Diagram www.onsemi.com 2 VBST 15 VDDL 5 LOSRC 6 LOSNK 7 PGND VDD 8 14